ALTERA DIGITAL LAB SOLUTIONS (DE1 Board)

Laboratory Exercise 1

Switches, Lights, and Multiplexers

PART1:

PROGRAM:

module part1(SW ,LEDR);
input [9:0]SW;
output [9:0]LEDR;
logic [9:0]LEDR;

assign LEDR=SW;

endmodule

TEST BENCH:

module part1_tb;
reg[9:0] sw;
wire[9:0] LEDR;
part1 p1(.sw(sw),.LEDR(LEDR));
initial 
begin
sw=10'd0;
#10
 sw=10'd0;
end
initial begin 
#100 $finish;
end
endmodule

PART 2:

PROGRAM:

module part2(x,y,s,m);
input [3:0]x,y;
input s;
output [3:0]m;

assign m =(~s & x) | (s & y);

endmodule

TEST BENCH:

module part2_tb();

logic [3:0] a,b; logic s; logic [3:0]y;
p1_2 t1(a,b,s,y);
initial begin a=4'b1000; b=4'b0100; s=0;
#5; s=1; end
initial begin $monitor("s=%d,y=%b",s,y); #50 $finish; endendmodule

PART 3:

PROGRAM:

module part3(a,b,c,s,z);

input [1:0]a,b,c,s;
output [1:0]z;
logic [1:0]y;

assign y[0]=(~s[0]&a[0]|s[0]&b[0]);
assign y[1]=(~s[0]&a[1]|s[0]&b[1]);

assign z[0]=(~s[1]&y[0]|s[1]&c[0]);
assign z[1]=(~s[1]&y[1]|s[1]&c[1]);

endmodule

TEST BENCH:

module part3_tb();
logic [1:0] a,b,c,s;
logic [1:0]z,y;

part3 t1(a,b,c,s,z);

initial begin
a=2'b10;
b=2'b11;
c=2'b01;
s[0]=0; s[1]=0;
#5;
s[0]=1; s[1]=0;
#5;
s[0]=0; s[1]=1;
#5;
s[0]=1; s[1]=1;
end

initial begin
$monitor("s=%b, z=%b ",s,z);
#50 $finish;
end
endmodule

PART 4:

PROGRAM:

module part4(a,b,c,s,z);

input [1:0]a,b,c,s;
output [1:0]z;
logic [1:0]y;

assign y[0]=(~s[0]&a[0]|s[0]&b[0]);
assign y[1]=(~s[0]&a[1]|s[0]&b[1]);

assign z[0]=(~s[1]&y[0]|s[1]&c[0]);
assign z[1]=(~s[1]&y[1]|s[1]&c[1]);

endmodule

TEST BENCH:

module part4_tb();
logic [1:0] a,b,c,s;
logic [1:0]z,y;

part4 t1(a,b,c,s,z);

initial begin
a=2'b10;
b=2'b11;
c=2'b01;
s[0]=0; s[1]=0;
#5;
s[0]=1; s[1]=0;
#5;
s[0]=0; s[1]=1;
#5;
s[0]=1; s[1]=1;
end

initial begin
$monitor("s=%b, z=%b ",s,z);
#50 $finish;
end
endmodule

PART 5:

PROGRAM:

module part5(a,b,c,s,out);
input [1:0]a,b,c,s;
logic s0,s1;
logic [1:0]y;
output [6:0]out[2:0];

assign y[0]=(~s[0]&a[0]|s[0]&b[0]);
assign y[1]=(~s[0]&a[1]|s[0]&b[1]);

assign s0=(~s[1]&y[0]|s[1]&c[0]);
assign s1=(~s[1]&y[1]|s[1]&c[1]);



assign out[0] = (s1?(s0?(7'b1111111):(7'b1111001)):(s0?(7'b0000110):(7'b0100001)));

assign out[1] = (s1?(s0?(7'b1111111):(7'b0100001)):(s0?(7'b1111001):(7'b0000110)));

assign out[2] = (s1?(s0?(7'b1111111):(7'b0000110)):(s0?(7'b0100001):(7'b1111001)));

endmodule

TEST BENCH:

module part5_tb();
logic [1:0]a,b,c,s;
logic [6:0]out[2:0];

part5 t1(a,b,c,s,out);

initial begin
a=2'b00;
b=2'b01;
c=2'b10;
s[1]=0; s[0]=0;
#5;
s[1]=0; s[0]=1;
#5;
s[1]=1; s[0]=0;
#5;
s[1]=1; s[0]=1;
end

initial begin
$monitor("out[0]=%b,out[1]=%b,out[2]=%b",out[0],out[1],out[2]);
#50 $finish;
end
endmodule

PART 6:

PROGRAM:

module part6(a,b,c,s,out);
input [1:0]a,b,c,s;
logic s0,s1;
logic [1:0]y;
output [6:0]out[3:0];

assign y[0]=(~s[0]&a[0]|s[0]&b[0]);
assign y[1]=(~s[0]&a[1]|s[0]&b[1]);

assign s0=(~s[1]&y[0]|s[1]&c[0]);
assign s1=(~s[1]&y[1]|s[1]&c[1]);



assign out[0] = (s1?(s0?(7'b1111001):(7'b0100001)):(s0?(7'b0000110):(7'b1111111)));

assign out[1] = (s1?(s0?(7'b1111111):(7'b1111001)):(s0?(7'b0100001):(7'b0000110)));

assign out[2] = (s1?(s0?(7'b0000110):(7'b1111111)):(s0?(7'b1111001):(7'b0100001)));

assign out[3] = (s1?(s0?(7'b0100001):(7'b0000110)):(s0?(7'b1111111):(7'b1111001)));

endmodule

TEST BENCH:

module part6_tb();
logic [1:0]a,b,c,s;
logic [6:0]out[3:0];

part6 t1(a,b,c,s,out);

initial begin
a=2'b00;
b=2'b01;
c=2'b10;
s[1]=0; s[0]=0;
#5;
s[1]=0; s[0]=1;
#5;
s[1]=1; s[0]=0;
#5;
s[1]=1; s[0]=1;
end

initial begin
$monitor("out[0]=%b,out[1]=%b,out[2]=%b,out[3]=%b",out[0],out[1],out[2],out[3]);
#50 $finish;
end
endmodule

About Group

              Many people are fascinated towards VLSI but don't know what to do or where to get info about a particular topic.After seeing many people we group of people thought to open a blog which will provide the basic info regarding not only on VLSI but also on different domains of electronics so that at least few people get benefit from our initiative and succeed in their dream field.

              This group mainly provides info from basics of Electronic Devices to almost every core topic of Electronics along with many available pdf files,videos,links of open source groups and also projects list of Minor,Major & IEEE standard.Whatever the codes available in this blog are not only simulated ones but are also synthesizable.The codes start from the basics of combinational circuits along with the latest ongoing IEEE projects in the industry.

               We hope this group forms a bridge between the freshers and the experts so that everyone can ask or suggest or provide possible info of the latest technologies.Apart from the queries if anyone wants the complete details of a project please post your email-id by commenting in the project list page.

                    
 We Wish Everyone Who Visits Our Blog May Feel Happy With Our Content