ALTERA DIGITAL LAB SOLUTIONS (DE1 Board)

Laboratory Exercise 3

Latches, Flip-flops, and Registers

PART 1:

PROGRAM:

module part1(clk,r,s,q);

input clk,r,s;

output [1:0]q;

logic a,b;


assign a = (clk&r);
assign b = (clk&s);

assign q[0] = ~(q[1]|a);
assign q[1] = ~(q[0]|b);
endmodule

TEST BENCH:

module part1_tb();

logic clk,r,s;
logic [1:0]q;

part1 p1(clk,r,s,q);

initial
clk=0;
always  #4 clk=~clk;


initial begin
r=0; s=0;
#5;
 r=1; s=0;
#5;
r=0; s=1;
#5;
r=1; s=1;
end

initial begin
$monitor ("r=%b,s=%b,clk=%b,q[0]=%b,q[1]=%b",r,s,clk,q[0],q[1]);
#100 $finish;
end
endmodule

PART 2:

PROGRAM:

module part2(clk,d,q);

input clk,d;
output [1:0]q;

logic a,b;

assign a = ~(clk&d);
assign b = ~(clk&~d);

assign q[0] = ~(a&q[1]);
assign q[1] = ~(b&q[0]);

endmodule

TEST BENCH:

module part2_tb();

logic clk,d;
logic [1:0]q;

ppart2 p3(clk,d,q);

initial
clk=0;
always #4 clk=~clk;

initial begin
d=0;
#10;
d=1;
end

initial begin
$monitor("d=%b,q[0]=%b,q[1]=%b",d,q[0],q[1]);
#50 $finish;
end
endmodule

PART 3:

PROGRAM:

///////Main Program/////

module part3(clk,d,q1,q2);
input clk,d;
output q1,q2;

wire c;

p_comp a1(~clk,d,c);
p_comp a2(clk,c,q1);

assign q2=~q1;

endmodule

///// component ///////

module p_comp(clk,d,q);

input clk,d;
output [1:0]q;

logic a,b;

assign a = ~(clk&d);
assign b = ~(clk&~d);

assign q[0] = ~(a&q[1]);
assign q[1] = ~(b&q[0]);
endmodule

TEST BENCH:

module part3_tb();

 reg clk,d;
 wire q1,q2;

part3 p1(clk,d,q1,q2);

initial
begin
d=0;
clk=0;
end
always #5 clk=~clk;

always #2 d=~d;

initial
begin
$monitor($time,"clk= %b d=%b,q1=%b,q2=%b",clk,d,q1,q2);
#50 $finish;
end
endmodule

PART 4:

PROGRAM:

module part4(d,clk,b,bbar);

input d,clk;
output  [2:0]b,bbar;

sample a1(d,clk,b[0]);
sample a2(d,clk,b[1]);
sample a3(d,~clk,b[2]);

assign bbar[0] = ~b[0];

assign bbar[1] = ~b[1];

assign bbar[2] = ~b[2];

endmodule

TEST BENCH:

module part4_tb();

reg d,clk;

wire [2:0]b;

part4 d1(d,clk,b,bbar);

initial begin

clk=0; d=0;

#5 d=1;
end

initial begin
 forever #5 clk=~clk;
end
 

initial begin
$monitor ("clk=%b,d=%b,b[0]=%b,b[1]=%b,b[2]=%b",clk,d,b[0],b[1],b[2]);

#50 $finish;
end
endmodule