VLSI ON NET

Tuesday, July 01, 2014

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AHB MASTER VERILOG CODE & TESTBENCH

CODE: module ahb_master(HBUSREQ,HLOCK,HTRANS,HADDR,HWRITE,HSIZE,HBURST,HWDATA,HSEL,HRESETn,HCLK,HGRANT,HREADY,HRESP,HRDATA,BUSREQ,ADDRE...
SYSTEM VERILOG PART-1

1. Introduction to System Verilog 1.1. System Verilog origins System Verilog is a standard set of extensions to the IEEE 1364...
ALTERA DIGITAL LAB SOLUTIONS (DE1 Board)

Laboratory Exercise 1 Switches, Lights, and Multiplexers PART1: PROGRAM: module part1(SW ,LEDR); input [9:0]SW; output [9:0]L...
Full Custom Memory Design Interview Questions

1. Explain the difference between Planar and FIN-FET technology ? 2. Explain pros and cons of gate length scales down ? 3. What is proc...
ALTERA DIGITAL LAB SOLUTIONS (DE1 Board)

Laboratory Exercise 3 Latches, Flip-ﬂops, and Registers PART 1: PROGRAM: module part1(clk,r,s,q); input clk,r,s; ...
ALTERA DIGITAL LAB SOLUTIONS (DE1 Board)

Laboratory Exercise 2 Numbers and Displays PART 1: PROGRAM: module part1(S0,S1,S2,S3,out); input [2:0]S0,S1,S2,S3; out...
About Group

Many people are fascinated towards VLSI but don't know what to do or where to get info about a particular topic.After se...
ASYNCHRONOUS FIFO

CODE: module a_fifo5(d_out,f_full_flag,f_half_full_flag,f_empty_flag, f_almost_full_flag,f_almost_empty_flag,d_in,r_en,w_en,r...
VERILOG BASICS

Design Methodology: There are two basic types of digital design methodologies: a top-down design methodology and a bottom-up desig...
VERILOG HDL SYNTHESIS Primer

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