LIST OF PROJECTS

VLSI MINI PROJECT LIST

1. Design of Free Floating point madness multiplier for Dsp applications. 
2.  Design of Sobel edge detector for communication.
3. Design of Delta sigma converter.
4. Design of Phase locked loop using verilog. 
5. Design of Floating point multiplier and adder /subtractor for multimedia applications. 
6. Design and implementation of Des s-box tables.
7. Design of Reed solemn encoder 
8. Design of Dual port Random access memory.
9. Design of signed integer multiplier
10. Design of unsigned integer multiplier
11. Design of linear feedback shift register used in built in self test.
12. Design of check sum generator and verifier
13. Design of parity generator and checker.
14. Design of cyclic redundancy checker
15. Design of fast page mode of dynamic random access memory controller
16. Design of static random access memory /read only memory controller
17. Design of hamming code
18. Design of 16 deep ram of 8bit
19. Design of synchronous FIFO
20. Design of direct digital frequency synthesizer.
21. Design of synchronizing FIFO
22. Design of simulation and synthesis of digital FM receiver using vhdl.
23. Design of 8 point fast Fourier transform for processing of multiple signals.
24. Design of A fast base 2 anti algorithm function  
25. New Adaptive Weight Algorithm for Salt & Pepper Noise Removal.
26. Removal of High Density salt & pepper noise Through Modified Decision Based Un-Symmetric Trimmed Median Filter.
27. Operation improvement of Indoor Robot By gesture Recognition.
28. Adiabatic Technique for Energy Efficient Logic Circuits Design.
29. Enhancing Efficiency In SRAM Array Through Recovery Boosting.
30. Design And FPGA Implementation of Modified Distributive Arithmetic Based DWT-IDWT Processor for Image compression.
31. Enhancing NBIT recovery in SRAM array through recovery boosting.
32. Optimization of processor  architecture for image edge detection filter
33. Design and analysis of TWO low-power  SRAM cell structure
34. A novel column-decoupled 8T cell for low power differential and domino-based SRAM design.
35. CMOS full adder for energy-efficient arithmetic application.
36. Pipelined architecture for FPGA implementation of lifting-based DWT.
37. Parallel architecture for hierarchical optical flow estimation based on FPGA.
38. A  VLSI architecture of SVC encoder for mobile system. 
39. Variability resilient low-power 7T SRAM design for Nano-scaled technologies.
40. Design and implement of the embedded elevator monitor system based on wireless communication.
41. A real time implementation of finger-robot interaction using FPGA.
42. Power estimation of embedded multiplier block in FPGAs
43. Flexible hardware architecture of hierarchical k-means clustering for large cluster number.
44. Keyless car entry through face recognition using FPGA.
45. Image edge detection based on FPGA.
46. Ground bounce noise reduction of low leakage 1-bit nano -cmos based full adder cells for mobile application.
47. Design of a low power flip-flop using cmos deep submicron technology.
48. Low-power and area- efficient carry select adder
49. A pipeline vlsi architecture for high-speed computation of the 1-d discrete wavelet transform.
50. FPGA based inexpensive automobile refuge System.
51. FPGA based inexpensive automobile refuge system
52. Sim card based smart banking using FPGA.
53. New Adaptive Weight Algorithm for Salt & Pepper Noise Removal.
54. Removal of High Density salt & pepper noise Through Modified Decision Based Un-Symmetric Trimmed Median Filter.
55. Operation improvement of Indoor Robot By gesture Recognition.
56. Adiabatic Technique for Energy Efficient Logic Circuits Design.
57. Enhancing Efficiency In SRAM Array Through Recovery Boosting.
58. Design And FPGA Implementation of Modified Distributive Arithmetic Based DWT-IDWT Processor for Image compression
59. Enhancing NBIT recovery in SRAM array through recovery boosting.
60. Optimization of processor  architecture for image edge detection filter
61. Design and analysis of TWO low-power  SRAM cell structure
62. A novel column-decoupled 8T cell for low power differential and domino-based SRAM design.
63. CMOS full adder for energy-efficient arithmetic application.
64. Pipelined architecture for FPGA implementation of lifting-based DWT.
65. Parallel architecture for hierarchical optical flow estimation based on FPGA.
66. A  VLSI architecture of SVC encoder for mobile system.
67. Variability resilient low-power 7T SRAM design for Nano-scaled technologies.
68. Design and implement of the embedded elevator monitor system based on wireless communication.
69. A real time implementation of finger-robot interaction using FPGA.
70. Power estimation of embedded multiplier block in FPGAs
71. Flexible hardware architecture of hierarchical k-means clustering for large cluster number.
72. Keyless car entry through face recognition using FPGA.
73. Ground bounce noise reduction of low leakage 1-bit nano -cmos based full adder cells for mobile application.
74. Design of a low power flip-flop using cmos deep submicron technology.
75. Low-power and area- efficient carry select adder
76. A pipeline vlsi architecture for high-speed computation of the 1-d discrete wavelet transform.
77. FPGA based inexpensive automobile refuge System.
78. FPGA based inexpensive automobile refuge system
79. Sim card based smart banking using FPGA