VHDL PROGRAMS:
Program 1: AND GATE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity gates is
port(a,b: in std_logic;
y: out std_logic);
end gates;
architecture gates of gates is
begin
y<= a and b;
end gates;
RTL AND TEST BENCH
TRUTH TABLE
A
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B
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Y
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1
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1
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0
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0
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1
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1
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY and_g11_vhd IS
END and_g11_vhd;
ARCHITECTURE behavior OF and_g11_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT and_g
PORT(
a : IN std_logic;
b : IN std_logic;
y : OUT std_logic
);
END COMPONENT;
--Inputs
SIGNAL a : std_logic := '0';
SIGNAL b : std_logic := '0';
--Outputs
SIGNAL y : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: and_g PORT MAP(
a => a,
b => b,
y => y
);
a<= '0' after 10 ns, b<= '1' after 10 ns;
a<= '1' after 20 ns, b<= '0' after 20 ns;
a<= '1' after 30 ns, b<= '1' after 30 ns;
END;
Program 2: OR GATE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity orgate is
port(a,b: in std_logic;
y : out std_logic);
end orgate;
architecture gates of orgate is
begin
y<= a or b;
end gates;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY or_test1 IS
END or_test1;
ARCHITECTURE behavior OF or_test1 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT or_test
PORT(
a : IN std_logic;
b : IN std_logic;
y : OUT std_logic
);
END COMPONENT;
--Inputs
signal a : std_logic := '0';
signal b : std_logic := '0';
--Outputs
signal y : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: or_test PORT MAP (
a => a,
b => b,
y => y
);
a<='0', '0' after 10 ns,'1' after 20 ns, '1' after 30 ns;
b<='0', '1' after 15 ns,'0' after 25 ns, '1' after 35 ns;
END;
Program 3: NOT GATE
RTL AND TEST BENCH
TRUTH TABLE
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B
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Y
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0
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0
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1
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1
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1
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY or_test1 IS
END or_test1;
ARCHITECTURE behavior OF or_test1 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT or_test
PORT(
a : IN std_logic;
b : IN std_logic;
y : OUT std_logic
);
END COMPONENT;
--Inputs
signal a : std_logic := '0';
signal b : std_logic := '0';
--Outputs
signal y : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: or_test PORT MAP (
a => a,
b => b,
y => y
);
a<='0', '0' after 10 ns,'1' after 20 ns, '1' after 30 ns;
b<='0', '1' after 15 ns,'0' after 25 ns, '1' after 35 ns;
END;
Program 3: NOT GATE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity notgate is
port(a: in std_logic;
y : out std_logic);
end notgate;
architecture gates of notgate is
begin
y<= not a;
end gates;
RTL AND TEST BENCH
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY nt_gate IS
END nt_gate;
ARCHITECTURE behavior OF nt_gate IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT or_test
PORT(
a : IN std_logic;
y : OUT std_logic
);
END COMPONENT;
--Inputs
signal a : std_logic := '0';
--Outputs
signal y : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: or_test PORT MAP (
a => a,
y => y
);
a<= '0','1' after 10 ns;
END;
RTL AND TEST BENCH
TRUTH TABLE
A
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Y
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0
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1
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1
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0
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY nt_gate IS
END nt_gate;
ARCHITECTURE behavior OF nt_gate IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT or_test
PORT(
a : IN std_logic;
y : OUT std_logic
);
END COMPONENT;
--Inputs
signal a : std_logic := '0';
--Outputs
signal y : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: or_test PORT MAP (
a => a,
y => y
);
a<= '0','1' after 10 ns;
END;
Program 4: NAND GATE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ndandgate is
port(a,b: in std_logic;
y : out std_logic);
end ndandgate;
architecture gates of ndandgate is
begin
y<= a nand b;
end gates;
RTL AND TEST BENCH
TRUTH TABLE
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY nand_gate11 IS
END nand_gate11;
ARCHITECTURE behavior OF nand_gate11 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT nand_gate1
PORT(
a : IN std_logic;
b : IN std_logic;
y : OUT std_logic
);
END COMPONENT;
--Inputs
signal a : std_logic := '0';
signal b : std_logic := '0';
--Outputs
signal y : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: nand_gate1 PORT MAP (
a => a,
b => b,
y => y
);
a<='0','0' after 100 ns, '1' after 200 ns, '1' after 300 ns;
b<='0','1' after 100 ns, '0' after 200 ns, '1' after 300 ns;
END;
RTL AND TEST BENCH
TRUTH TABLE
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A
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B
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Y
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0
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0
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0
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1
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY nand_gate11 IS
END nand_gate11;
ARCHITECTURE behavior OF nand_gate11 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT nand_gate1
PORT(
a : IN std_logic;
b : IN std_logic;
y : OUT std_logic
);
END COMPONENT;
--Inputs
signal a : std_logic := '0';
signal b : std_logic := '0';
--Outputs
signal y : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: nand_gate1 PORT MAP (
a => a,
b => b,
y => y
);
a<='0','0' after 100 ns, '1' after 200 ns, '1' after 300 ns;
b<='0','1' after 100 ns, '0' after 200 ns, '1' after 300 ns;
END;
Program 5: NOR GATE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity norgate is
port(a,b: in std_logic;
y : out std_logic);
end norgate;
architecture gates of norgate is
begin
y<= a nor b;
end gates;
RTL AND TEST BENCH
TRUTH TABLE
RTL AND TEST BENCH
TRUTH TABLE
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A
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B
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Y
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0
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0
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1
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Program 6: XOR GATE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity xorgate is
port(a,b: in std_logic;
y : out std_logic);
end xorgate;
architecture gates of xorgate is
begin
y<= a xor b;
end gates;
Program 7: XNOR GATE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity xnorgate is
port(a,b: in std_logic;
y : out std_logic);
end xnorgate;
architecture gates of xnorgate is
begin
y<= a xnor b;
end gates;
Program 8: HALF ADDER
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity adder is
port(a,b: in std_logic;
sum,carry: out std_logic);
end adder;
architecture adder of adder is
begin
sum<= a xor b;
carry<= a and b;
end adder;
Program 9: FULL ADDER
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fadder is
port(a,b,cin: in std_logic;
sum,carry: out std_logic);
end fadder;
architecture fadder of fadder is
begin
sum<= a xor b xor cin;
carry<= (a and b) or (b and cin) or (cin
and a);
end fadder;
Program 10: 2:1 MUX
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux1 is
port(i0,i1: in std_logic;
sel: in std_logic;
y : out std_logic);
end mux1;
architecture mux1 of mux1 is
begin
process(sel)
begin
if( sel ='0') then
y<= i0;
else
y<=i1;
end if;
Program 11: 4:1 MUX (Using IF and ELSE)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux4 is
port(a:
in std_logic_vector(3 downto 0);
s: in std_logic_vector(1 downto 0);
y: out std_logic);
end mux4;
architecture behavioral of mux4 is
begin
process(s)
begin
if
(s="00")then
y<= a(0);
elsif(s="01")then
y<=a(1);
elsif (s="10")then
y<=a(2);
else
y<=a(3);
end
if;
end process;
end behavioral;
Program 12: 4:1 MUX (Using CASE)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux4 is
port(a:
in std_logic_vector(3 downto 0);
s: in std_logic_vector(1 downto 0);
y: out std_logic);
end mux4;
architecture behavioral of mux4 is
begin
process(s)
begin
case s is
when "00"=> y<= a(0);
when "01"=> y<= a(1);
when "10"=> y<= a(2);
when others=> y<= a(3);
end
case;
end
process;
end behavioral;
Program 13: 8:1 MUX (Using IF and Else)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux8 is
port(a: in std_logic_vector(0 to 7);
s: in std_logic_vector(0 to 2);
y: out std_logic);
end mux8;
architecture mux8 of mux8 is
begin
process(s)
begin
if(s="000") then
y<= a(0);
elsif(s="001") then
y<= a(1);
elsif(s="010") then
y<= a(2);
elsif(s="011") then
y<= a(3);
elsif(s="100") then
y<= a(4);
elsif(s="101") then
y<= a(5);
elsif(s="110") then
y<= a(6);
else
y<= a(7);
end if;
end process;
end mux8;
Program 14: 8:1 MUX (Using CASE)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux81 is
port(a: in std_logic_vector(0 to 7);
s: in std_logic_vector(0 to 2);
y: out std_logic);
end mux81;
architecture mux8 of mux81 is
begin
process(s)
begin
case s is
when "000"=> y<=a(0);
when "001"=> y<=a(1);
when "010"=> y<=a(2);
when "011"=> y<=a(3);
when "100"=> y<=a(4);
when "101"=> y<=a(5);
when "110"=> y<=a(6);
when others=> y<=a(0);
end case;
end process;
Program 15: 4:2 ENCODER
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity encode is
port(a: in std_logic_vector(0 to 3);
y: out std_logic_vector(0 to 1));
end encode;
architecture encode of encode is
begin
y<="00" when
a="0001" else
"01" when a="0010" else
"10" when a="0100" else
"11" when a="1000";
end encode;
Program 16: D LATCH
Program 17: D FLIP-FLOP
Program 16: D LATCH
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dlatch is
Port ( gate : in STD_LOGIC;
data : in STD_LOGIC;
q : out STD_LOGIC);
end dlatch;
architecture Behavioral of dlatch is
begin
latch:process(gate,data)
begin
if(gate='1')
then
q<=data;
end if;
end process;
end Behavioral;Program 17: D FLIP-FLOP
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dff is
Port ( d : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC;
qbar : out STD_LOGIC);
end dff;
architecture Behavioral of dff is
signal t1:std_logic;
begin
process(clk)
begin
if(clk'event and clk='1')
then
t1<=d;
end if;
end process;
q<=t1;
qbar<=not t1;
end Behavioral;
Program 18: D FLIP-FLOP WITH RESET
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dff_rst is
Port ( d : in STD_LOGIC;
rst : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC;
qbar : out STD_LOGIC);
end dff_rst;
architecture Behavioral of dff_rst is
signal t1:std_logic;
begin
process(rst,clk)
begin
if(rst='1')
then
t1<='0';
elsif(clk'event and clk='1')
then
t1<=d;
end if;
end process;
q<=t1;
qbar<=not t1;
end Behavioral;
Program 19: JK FLIP-FLOP
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity jkff1 is
Port ( clk : in STD_LOGIC;
j : in STD_LOGIC;
k : in STD_LOGIC;
q : out STD_LOGIC);
end jkff1;
architecture Behavioral of jkff1 is
signal jk:std_logic_vector(1 downto 0);
signal s:std_logic;
begin
jk<=j&k;
process(clk,j,k)
begin
if(clk'event and clk='1')then
case jk is
when "00"=> s<=s;
when "01"=> s<='0';
when "10"=> s<='1';
when "11"=> s<=not s;
when others=> s<=s;
end case;
end if;
end process;
q<=s;
end Behavioral;
Program 20: T FLIP-FLOP
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity tff is
Port ( t,rst : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC;
qbar : out STD_LOGIC);
end tff;
architecture Behavioral of tff is
signal s:std_logic;
begin
process(rst,t,clk)
begin
if(rst='1')then
s<='0';
elsif(clk'event and clk='1')
then
s<= not t;
end if;
end process;
q<=s;
qbar<=not s;
end Behavioral;
Program 21: SR FLIP-FLOP
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity srff is
Port ( s : in STD_LOGIC_VECTOR (1
downto 0);
clk : in STD_LOGIC;
q : out STD_LOGIC;
qbar : out STD_LOGIC);
end srff;
architecture Behavioral of srff is
signal t1:std_logic;
begin
process(s,clk)
begin
if(clk'event and clk='1')
then
case s is
when "00" => t1<=t1;
when "01" => t1<='0';
when "10" => t1<='1';
when others => t1<='Z';
end case;
end if;
end process;
q<=t1;
qbar<=not t1;
end Behavioral;
Program 22: TRISTATE BUFFER (1-BIT)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.All;
entity tristatebuffer is
Port ( input : in STD_LOGIC;
enable : in STD_LOGIC;
output : inout STD_LOGIC);
end tristatebuffer;
architecture Behavioral of tristatebuffer
is
begin
process(input,enable)
begin
if(enable='1')
then output<=input;
else output<='Z';
end if;
end process;
end Behavioral;
Program 23: TRISTATE BUFFER (8-BIT)
Program 24: 4-BIT RING COUNTER
--Library declaration.
library ieee;
use ieee.std_logic_1164.all;
--4 bit Parallel In Serial Out shift register(LSB is out first)
entity PISO is
port ( Serial_out : out std_logic;
Parallel_In : in std_logic_vector(3 downto 0);
--Load=1 means register is loaded parallely and Load=0 means right shift by one bit.
Load : in std_logic;
Clk : in std_logic
);
end PISO;
architecture gate_level of PISO is
signal D,Q,Load_value : std_logic_vector(3 downto 0):="0000";
signal i : integer := 0;
begin
Load_value <= Parallel_In;
Serial_out <= Q(3);
--entity instantiation of the D flipflop using "generate".
F : --label name
for i in 0 to 3 generate --D FF is instantiated 4 times.
begin --"begin" statement for "generate"
FDRSE_inst : entity work.example_FDRSE port map --usual port mapping
(Q => Q(i),
CLK => Clk,
CE => '1',
RESET => '0',
D => D(i),
SET => '0');
end generate F; --end "generate" block.
--The D inputs of the flip flops are controlled with the load input.
--Two AND gates with a OR gate is used for this.
D(0) <= Load_value(3) and Load;
D(1) <= (Load_value(2) and Load) or (Q(0) and not(Load));
D(2) <= (Load_value(1) and Load) or (Q(1) and not(Load));
D(3) <= (Load_value(0) and Load) or (Q(2) and not(Load));
end gate_level;
--Library declaration.
library ieee;
use ieee.std_logic_1164.all;
--4 bit Parallel In Serial Out shift register(LSB is out first)
entity PISO is
port ( Serial_out : out std_logic;
Parallel_In : in std_logic_vector(3 downto 0);
--Load=1 means register is loaded parallely and Load=0 means right shift by one bit.
Load : in std_logic;
Clk : in std_logic
);
end PISO;
architecture gate_level of PISO is
signal D,Q,Load_value : std_logic_vector(3 downto 0):="0000";
signal i : integer := 0;
begin
Load_value <= Parallel_In;
Serial_out <= Q(3);
--entity instantiation of the D flipflop using "generate".
F : --label name
for i in 0 to 3 generate --D FF is instantiated 4 times.
begin --"begin" statement for "generate"
FDRSE_inst : entity work.example_FDRSE port map --usual port mapping
(Q => Q(i),
CLK => Clk,
CE => '1',
RESET => '0',
D => D(i),
SET => '0');
end generate F; --end "generate" block.
--The D inputs of the flip flops are controlled with the load input.
--Two AND gates with a OR gate is used for this.
D(0) <= Load_value(3) and Load;
D(1) <= (Load_value(2) and Load) or (Q(0) and not(Load));
D(2) <= (Load_value(1) and Load) or (Q(1) and not(Load));
D(3) <= (Load_value(0) and Load) or (Q(2) and not(Load));
end gate_level;
Program 31: DIVISION TWO SIGNED NUMBERS
USING FUNCTION:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity tristatebuffer8 is
Port ( input : in
STD_LOGIC_VECTOR (7 downto 0);
enable : in STD_LOGIC;
output : out STD_LOGIC_VECTOR (7
downto 0));
end tristatebuffer8;
architecture Behavioral of tristatebuffer8
is
begin
process(input,enable)
begin
if(enable='1')
then
output<=input;
else
output<="ZZZZZZZZ";
end if;
end process;
end Behavioral;
Program 24: 4-BIT RING COUNTER
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ring_counter is
port (
DAT_O : out unsigned(3 downto 0);
RST_I : in std_logic;
CLK_I : in std_logic
);
end ring_counter;
architecture Behavioral of ring_counter is
signal temp : unsigned(3 downto 0):=(others => '0');
begin
DAT_O <= temp;
process(CLK_I)
begin
if( rising_edge(CLK_I) ) then
if (RST_I = '1') then
temp <= (0=> '1', others => '0');
else
temp(1) <= temp(0);
temp(2) <= temp(1);
temp(3) <= temp(2);
temp(0) <= temp(3);
end if;
end if;
end process;
end Behavioral;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ring_counter is
port (
DAT_O : out unsigned(3 downto 0);
RST_I : in std_logic;
CLK_I : in std_logic
);
end ring_counter;
architecture Behavioral of ring_counter is
signal temp : unsigned(3 downto 0):=(others => '0');
begin
DAT_O <= temp;
process(CLK_I)
begin
if( rising_edge(CLK_I) ) then
if (RST_I = '1') then
temp <= (0=> '1', others => '0');
else
temp(1) <= temp(0);
temp(2) <= temp(1);
temp(3) <= temp(2);
temp(0) <= temp(3);
end if;
end if;
end process;
end Behavioral;
Program 25: BCD TO 7-SEGMENT DISPLAY CONVERTER
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity test is
port (
clk : in std_logic;
bcd : in std_logic_vector(3 downto 0); --BCD input
segment7 : out std_logic_vector(6 downto 0) -- 7 bit decoded output.
);
end test;
--'a' corresponds to MSB of segment7 and g corresponds to LSB of segment7.
architecture Behavioral of test is
begin
process (clk,bcd)
BEGIN
if (clk'event and clk='1') then
case bcd is
when "0000"=> segment7 <="0000001"; -- '0'
when "0001"=> segment7 <="1001111"; -- '1'
when "0010"=> segment7 <="0010010"; -- '2'
when "0011"=> segment7 <="0000110"; -- '3'
when "0100"=> segment7 <="1001100"; -- '4'
when "0101"=> segment7 <="0100100"; -- '5'
when "0110"=> segment7 <="0100000"; -- '6'
when "0111"=> segment7 <="0001111"; -- '7'
when "1000"=> segment7 <="0000000"; -- '8'
when "1001"=> segment7 <="0000100"; -- '9'
--nothing is displayed when a number more than 9 is given as input.
when others=> segment7 <="1111111";
end case;
end if;
end process;
end Behavioral;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity test is
port (
clk : in std_logic;
bcd : in std_logic_vector(3 downto 0); --BCD input
segment7 : out std_logic_vector(6 downto 0) -- 7 bit decoded output.
);
end test;
--'a' corresponds to MSB of segment7 and g corresponds to LSB of segment7.
architecture Behavioral of test is
begin
process (clk,bcd)
BEGIN
if (clk'event and clk='1') then
case bcd is
when "0000"=> segment7 <="0000001"; -- '0'
when "0001"=> segment7 <="1001111"; -- '1'
when "0010"=> segment7 <="0010010"; -- '2'
when "0011"=> segment7 <="0000110"; -- '3'
when "0100"=> segment7 <="1001100"; -- '4'
when "0101"=> segment7 <="0100100"; -- '5'
when "0110"=> segment7 <="0100000"; -- '6'
when "0111"=> segment7 <="0001111"; -- '7'
when "1000"=> segment7 <="0000000"; -- '8'
when "1001"=> segment7 <="0000100"; -- '9'
--nothing is displayed when a number more than 9 is given as input.
when others=> segment7 <="1111111";
end case;
end if;
end process;
end Behavioral;
Program 26: CYCLIC REDUNDANCY CHECK (CRC)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity crc32_8 is port ( clk : in std_logic;
data_in : in std_logic_vector(31 downto 0);
crcout : out std_logic_vector(7 downto 0)
); end crc32_8; architecture Behavioral of crc32_8 is
signal crc_temp : std_logic_vector(7 downto 0) := "00000000"; signal counter1 : std_logic_vector(5 downto 0):="000000"; signal dtemp : std_logic_vector(31 downto 0):=(others => '0'); begin
dtemp <= data_in; process(data_in,clk) begin
if(data_in /= "00000000000000000000000000000000") then if(clk'event and clk='1') then --CRC calculation. Function used is : X^8 + X^2 + X^1 +1. --Edit the next 8 lines to compute a different CRC function.
crc_temp(0) <= data_in(31-conv_integer(counter1(4 downto 0))) xor crc_temp(7);
crc_temp(1) <= data_in(31-conv_integer(counter1(4 downto 0))) xor crc_temp(7) xor crc_temp(0);
crc_temp(2) <= data_in(31-conv_integer(counter1(4 downto 0))) xor crc_temp(7) xor crc_temp(1);
crc_temp(3) <= crc_temp(2);
crc_temp(4) <= crc_temp(3);
crc_temp(5) <= crc_temp(4);
crc_temp(6) <= crc_temp(5);
crc_temp(7) <= crc_temp(6); --CRC calculation is finished here. --counter increment.
counter1 <= counter1 + '1'; end if;
if(counter1 ="100000") then --counter for doing the CRC operation for 8 times.
crcout <= crc_temp;
crc_temp <="00000000";
counter1 <= "000000"; else
crcout <= "00000000"; --CRC output is zero during idle time. end if; else
--CRC output is zero when input is not given or input is zero
crcout <= "00000000";
crc_temp <="00000000";
counter1 <= "000000"; end if; end process;
end Behavioral;
entity crc32_8 is port ( clk : in std_logic;
data_in : in std_logic_vector(31 downto 0);
crcout : out std_logic_vector(7 downto 0)
); end crc32_8; architecture Behavioral of crc32_8 is
signal crc_temp : std_logic_vector(7 downto 0) := "00000000"; signal counter1 : std_logic_vector(5 downto 0):="000000"; signal dtemp : std_logic_vector(31 downto 0):=(others => '0'); begin
dtemp <= data_in; process(data_in,clk) begin
if(data_in /= "00000000000000000000000000000000") then if(clk'event and clk='1') then --CRC calculation. Function used is : X^8 + X^2 + X^1 +1. --Edit the next 8 lines to compute a different CRC function.
crc_temp(0) <= data_in(31-conv_integer(counter1(4 downto 0))) xor crc_temp(7);
crc_temp(1) <= data_in(31-conv_integer(counter1(4 downto 0))) xor crc_temp(7) xor crc_temp(0);
crc_temp(2) <= data_in(31-conv_integer(counter1(4 downto 0))) xor crc_temp(7) xor crc_temp(1);
crc_temp(3) <= crc_temp(2);
crc_temp(4) <= crc_temp(3);
crc_temp(5) <= crc_temp(4);
crc_temp(6) <= crc_temp(5);
crc_temp(7) <= crc_temp(6); --CRC calculation is finished here. --counter increment.
counter1 <= counter1 + '1'; end if;
if(counter1 ="100000") then --counter for doing the CRC operation for 8 times.
crcout <= crc_temp;
crc_temp <="00000000";
counter1 <= "000000"; else
crcout <= "00000000"; --CRC output is zero during idle time. end if; else
--CRC output is zero when input is not given or input is zero
crcout <= "00000000";
crc_temp <="00000000";
counter1 <= "000000"; end if; end process;
end Behavioral;
Program 27: DIGITAL CLOCK
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity digi_clk is port (clk1 : in std_logic;
seconds : out std_logic_vector(5 downto 0);
minutes : out std_logic_vector(5 downto 0);
hours : out std_logic_vector(4 downto 0)
); end digi_clk;
architecture Behavioral of digi_clk is signal sec,min,hour : integer range 0 to 60 :=0; signal count : integer :=1; signal clk : std_logic :='0'; begin
seconds <= conv_std_logic_vector(sec,6);
minutes <= conv_std_logic_vector(min,6);
hours <= conv_std_logic_vector(hour,5);
--clk generation.For 100 MHz clock this generates 1 Hz clock. process(clk1) begin if(clk1'event and clk1='1') then
count <=count+1; if(count = 50000000) then
clk <= not clk;
count <=1; end if; end if; end process;
process(clk) --period of clk is 1 second. begin
if(clk'event and clk='1') then
sec <= sec+ 1; if(sec = 59) then
sec<=0;
min <= min + 1; if(min = 59) then
hour <= hour + 1;
min <= 0; if(hour = 23) then
hour <= 0; end if; end if; end if; end if; end process;
end Behavioral;
entity digi_clk is port (clk1 : in std_logic;
seconds : out std_logic_vector(5 downto 0);
minutes : out std_logic_vector(5 downto 0);
hours : out std_logic_vector(4 downto 0)
); end digi_clk;
architecture Behavioral of digi_clk is signal sec,min,hour : integer range 0 to 60 :=0; signal count : integer :=1; signal clk : std_logic :='0'; begin
seconds <= conv_std_logic_vector(sec,6);
minutes <= conv_std_logic_vector(min,6);
hours <= conv_std_logic_vector(hour,5);
--clk generation.For 100 MHz clock this generates 1 Hz clock. process(clk1) begin if(clk1'event and clk1='1') then
count <=count+1; if(count = 50000000) then
clk <= not clk;
count <=1; end if; end if; end process;
process(clk) --period of clk is 1 second. begin
if(clk'event and clk='1') then
sec <= sec+ 1; if(sec = 59) then
sec<=0;
min <= min + 1; if(min = 59) then
hour <= hour + 1;
min <= 0; if(hour = 23) then
hour <= 0; end if; end if; end if; end if; end process;
end Behavioral;
Program 28: JOHNSON COUNTER
--Library declaration.
library ieee;
use ieee.std_logic_1164.all;
--4 bit Parallel In Serial Out shift register(LSB is out first)
entity PISO is
port ( Serial_out : out std_logic;
Parallel_In : in std_logic_vector(3 downto 0);
--Load=1 means register is loaded parallely and Load=0 means right shift by one bit.
Load : in std_logic;
Clk : in std_logic
);
end PISO;
architecture gate_level of PISO is
signal D,Q,Load_value : std_logic_vector(3 downto 0):="0000";
signal i : integer := 0;
begin
Load_value <= Parallel_In;
Serial_out <= Q(3);
--entity instantiation of the D flipflop using "generate".
F : --label name
for i in 0 to 3 generate --D FF is instantiated 4 times.
begin --"begin" statement for "generate"
FDRSE_inst : entity work.example_FDRSE port map --usual port mapping
(Q => Q(i),
CLK => Clk,
CE => '1',
RESET => '0',
D => D(i),
SET => '0');
end generate F; --end "generate" block.
--The D inputs of the flip flops are controlled with the load input.
--Two AND gates with a OR gate is used for this.
D(0) <= Load_value(3) and Load;
D(1) <= (Load_value(2) and Load) or (Q(0) and not(Load));
D(2) <= (Load_value(1) and Load) or (Q(1) and not(Load));
D(3) <= (Load_value(0) and Load) or (Q(2) and not(Load));
end gate_level;
Program 29: PISO USING FLIP-FLOPS
--Library declaration.
library ieee;
use ieee.std_logic_1164.all;
--4 bit Parallel In Serial Out shift register(LSB is out first)
entity PISO is
port ( Serial_out : out std_logic;
Parallel_In : in std_logic_vector(3 downto 0);
--Load=1 means register is loaded parallely and Load=0 means right shift by one bit.
Load : in std_logic;
Clk : in std_logic
);
end PISO;
architecture gate_level of PISO is
signal D,Q,Load_value : std_logic_vector(3 downto 0):="0000";
signal i : integer := 0;
begin
Load_value <= Parallel_In;
Serial_out <= Q(3);
--entity instantiation of the D flipflop using "generate".
F : --label name
for i in 0 to 3 generate --D FF is instantiated 4 times.
begin --"begin" statement for "generate"
FDRSE_inst : entity work.example_FDRSE port map --usual port mapping
(Q => Q(i),
CLK => Clk,
CE => '1',
RESET => '0',
D => D(i),
SET => '0');
end generate F; --end "generate" block.
--The D inputs of the flip flops are controlled with the load input.
--Two AND gates with a OR gate is used for this.
D(0) <= Load_value(3) and Load;
D(1) <= (Load_value(2) and Load) or (Q(0) and not(Load));
D(2) <= (Load_value(1) and Load) or (Q(1) and not(Load));
D(3) <= (Load_value(0) and Load) or (Q(2) and not(Load));
end gate_level;
Program 30: SINE WAVE GENERATOR
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL; --try to use this library as much as possible.
entity sinewave is port (clk :in std_logic;
dataout : out integer range -128 to 127
); end sinewave;
architecture Behavioral of sinewave is signal i : integer range 0 to 30:=0; type memory_type is array (0 to 29) of integer range -128 to 127; --ROM for storing the sine values generated by MATLAB. signal sine : memory_type :=(0,16,31,45,58,67,74,77,77,74,67,58,45,31,16,0,
-16,-31,-45,-58,-67,-74,-77,-77,-74,-67,-58,-45,-31,-16);
begin
process(clk) begin
--to check the rising edge of the clock signal if(rising_edge(clk)) then
dataout <= sine(i);
i <= i+ 1; if(i = 29) then
i <= 0; end if; end if; end process; end Behavioral;
entity sinewave is port (clk :in std_logic;
dataout : out integer range -128 to 127
); end sinewave;
architecture Behavioral of sinewave is signal i : integer range 0 to 30:=0; type memory_type is array (0 to 29) of integer range -128 to 127; --ROM for storing the sine values generated by MATLAB. signal sine : memory_type :=(0,16,31,45,58,67,74,77,77,74,67,58,45,31,16,0,
-16,-31,-45,-58,-67,-74,-77,-77,-74,-67,-58,-45,-31,-16);
begin
process(clk) begin
--to check the rising edge of the clock signal if(rising_edge(clk)) then
dataout <= sine(i);
i <= i+ 1; if(i = 29) then
i <= 0; end if; end if; end process; end Behavioral;
Program 31: DIVISION TWO SIGNED NUMBERS
USING FUNCTION:
function divide (a : UNSIGNED; b : UNSIGNED) return UNSIGNED is
variable a1 : unsigned(a'length-1 downto 0):=a;
variable b1 : unsigned(b'length-1 downto 0):=b;
variable p1 : unsigned(b'length downto 0):= (others => '0');
variable i : integer:=0;
begin
for i in 0 to b'length-1 loop
p1(b'length-1 downto 1) := p1(b'length-2 downto 0);
p1(0) := a1(a'length-1);
a1(a'length-1 downto 1) := a1(a'length-2 downto 0);
p1 := p1-b1;
if(p1(b'length-1) ='1') then
a1(0) :='0';
p1 := p1+b1;
else
a1(0) :='1';
end if;
end loop;
return a1;
end divide;
variable a1 : unsigned(a'length-1 downto 0):=a;
variable b1 : unsigned(b'length-1 downto 0):=b;
variable p1 : unsigned(b'length downto 0):= (others => '0');
variable i : integer:=0;
begin
for i in 0 to b'length-1 loop
p1(b'length-1 downto 1) := p1(b'length-2 downto 0);
p1(0) := a1(a'length-1);
a1(a'length-1 downto 1) := a1(a'length-2 downto 0);
p1 := p1-b1;
if(p1(b'length-1) ='1') then
a1(0) :='0';
p1 := p1+b1;
else
a1(0) :='1';
end if;
end loop;
return a1;
end divide;
The function can be used as follows in your main module:
--An example of how to use the function.
signal a : unsigned(7 downto 0) :="10011100";
signal b : unsigned(7 downto 0) :="00001010";
signal c : unsigned(7 downto 0) :=(others => '0');
c <= divide ( a , b ); --function is "called" here.
For using the function you have to copy the code snippet between the green lines and put it in a package.The libraries I have used are given below:
c <= divide ( a , b ); --function is "called" here.
For using the function you have to copy the code snippet between the green lines and put it in a package.The libraries I have used are given below:
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all; -- for UNSIGNED
use ieee.numeric_std.all; -- for UNSIGNED
WITHOUT USING FUNCTIONS:
--An example for a module using package..
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--note this line.The package is compiled to this directory by default. --so don't forget to include this directory. library work; --this line also is must.This includes the particular package into your program. use work.test_pkg.all;
entity test is port (clk : in std_logic;
a1 : in t1;
b1 : in t1;
c1: out t1
); end test;
architecture Behavioral of test is begin process(clk) begin if(clk'event and clk='1') then
c1<=add(a1,b1); --for doing xor operation at every positive edge of clock cycle. end if; end process; end Behavioral;
--Package declaration for the above program library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all;
package test_pkg is type t1 is --a data type(totally 32 bits contains 3 different fields)
record
a :std_logic_vector(11 downto 0);
b :std_logic_vector(15 downto 0);
c :std_logic_vector(3 downto 0);
end record;
--function declaration. function add (a2 : t1; b2: t1) return t1; end test_pkg; --end of package.
package body test_pkg is --start of package body --definition of function function add (a2 : t1; b2: t1) return t1 is variable sum : t1; begin -- Just name the fields in order...
sum.a:=a2.a xoR b2.a;
sum.b:=a2.b xoR b2.b;
sum.c:=a2.c xoR b2.c; return sum; end add; --end function end test_pkg; --end of the package body
--note this line.The package is compiled to this directory by default. --so don't forget to include this directory. library work; --this line also is must.This includes the particular package into your program. use work.test_pkg.all;
entity test is port (clk : in std_logic;
a1 : in t1;
b1 : in t1;
c1: out t1
); end test;
architecture Behavioral of test is begin process(clk) begin if(clk'event and clk='1') then
c1<=add(a1,b1); --for doing xor operation at every positive edge of clock cycle. end if; end process; end Behavioral;
--Package declaration for the above program library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all;
package test_pkg is type t1 is --a data type(totally 32 bits contains 3 different fields)
record
a :std_logic_vector(11 downto 0);
b :std_logic_vector(15 downto 0);
c :std_logic_vector(3 downto 0);
end record;
--function declaration. function add (a2 : t1; b2: t1) return t1; end test_pkg; --end of package.
package body test_pkg is --start of package body --definition of function function add (a2 : t1; b2: t1) return t1 is variable sum : t1; begin -- Just name the fields in order...
sum.a:=a2.a xoR b2.a;
sum.b:=a2.b xoR b2.b;
sum.c:=a2.c xoR b2.c; return sum; end add; --end function end test_pkg; --end of the package body
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