VLSI ON NET: VERILOG

PROGRAMS

Program 1: AND Gate

module gate_and(a,b, c);
    input a,b;
    output c;
    reg c;
always @ (a,b)
   begin
   c <= a & b;
   end
endmodule

Program 2: OR Gate

module gate_or(a,b, c);
    input a,b;
    output c;
    reg c;
always @ (a,b)
   begin
   c <= a || b;
   end
endmodule

Program 3: NOT Gate

module gate_not(a,b);
    input a;
    output b;
    reg b;
always @ (a)
   begin
   b <= ~a;
   end
endmodule

Program 4: NAND Gate

module gate_nand(a,b, c);
    input a,b;
    output c;
    reg c;
always @ (a,b)
   begin
   c <= ~(a & b);
   end
endmodule

Program 5: NOR Gate

module gate_nor(a,b,c);
    input a,b;
    output c;
    reg c;
always @ (a,b)
   begin
   c<=~(a || b);
   end
endmodule

Program 6:XOR Gate

module gate_xor(a,b,c);
    input a,b;
    output c;
    reg c;
always @ (a,b)
   begin
   c<=(a^b);
   end
endmodule

Program 7:XNOR Gate

module gate_xor(a,b,c);
    input a,b;
    output c;
    reg c;
always @ (a,b)
   begin
   c<=~(a^b);
   end
endmodule

Program 8:HALF ADDER

module h_add(a,b, sum,carry);
    input a,b;
    output sum,carry;
    reg sum,carry;
always @ (a,b)
    begin
    sum<=(a^b);
    carry<= (a&b);
    end
endmodule

Program 9:FULL ADDER

module h_add(a,b,cin,sum,carry);
    input a,b,cin;
    output sum,carry;
    reg sum,carry;
always @ (a,b,cin)
    begin
    sum<=(a^b^cin);
    carry<= (a&b)||(b&cin)||(a&cin);
    end
endmodule

Program 10: D-LATCH WITH A POSITIVE GATE

module latch (g, d, q);

input g, d;

output q;

reg q;

always @(g or d)

begin

if (g)

q <= d;

end

endmodule

Program 11:D-LATCH WITH A POSITIVE GATE AND AN ASYNCHRONOUS CLEAR

module latch (g, d, clr, q);

input g, d, clr;

output q;

reg q;

always @(g or d or clr)

begin

if (clr)

q <= 1'b0;

else if (g)

q <= d;

end

endmodule

Program 12: 4-BIT LATCH WITH AN INVERTED GATE AND ASYNCHRONOUS PRESET

module latch (g, d, pre, q);

input g, pre;

input [3:0] d;

output [3:0] q;

reg [3:0] q;

always @(g or d or pre)

begin

if (pre)

q <= 4'b1111;

else if (~g)

q <= d;

end

endmodule

Program 13:D-FLIP FLOP WITH NEGATIVE EDGE CLOK AND ASYNCRHONOUS CLEAR

module flop(clk, d, clr, q);

input clk, d, clr;

output q;

reg q;

always @(negedge clk or posedge clr)

begin

if (clr)

q <= 1'b0;

else

q <= d;

end

endmodule

Program 14:D-FLIP FLOP WITH POSITIVE EDGE CLOK AND SYNCRHONOUS SET

module flop (clk, d, s, q);

input clk, d, s;

output q;

reg q;

always @(posedge clk)

begin

if (s)

q <= 1'b1;

else

q <= d;

end

endmodule

Program 15:D-FLIP FLOP WITH POSITIVE EDGE CLOK AND CLOCK ENABLE

module flop (clk, d, ce, q);

input clk, d, ce;

output q;

reg q;

always @(posedge clk)

begin

if (ce)

q <= d;

end

endmodule

Program 16: 4-BIT REGISTER WITH A POSITIVE EDGE CLOCK, SYNCHRONOUS SET AND CLOCK ENABLE

module flop (clk, d, ce, pre, q);

input clk, ce, pre;

input [3:0] d;

output [3:0] q;

reg [3:0] q;

always @(posedge clk or posedge pre)

begin

if (pre)

q <= 4'b1111;

else if (ce)

q <= d;

end

endmodule

Program 17: TRI-STATE BUFFER

module three_st (t, i, o);

input t, i;

output o;

reg o;

always @(t or i)

begin

if (~t)

o = i;

else

o = 1'bZ;

end

endmodule

Program 18:TRI-STATE BUFFER USING CONDITIONAL OPERATORS (USING CONCURRENT ASSIGNMENTS)

module three_st (t, i, o);

input t, i;

output o;

assign o = (~t) ? i: 1'bZ;

endmodule

Program 19: 4-BIT UNSIGNED UP COUNTER WITH ASYNCHRONUOS CLEAR

module counter (clk, clr, q);

input clk, clr;

output [3:0] q;

reg [3:0] tmp;

always @(posedge clk or posedge clr)

begin

if (clr)

tmp <= 4'b0000;

else

tmp <= tmp + 1'b1;

end

assign q = tmp;

endmodule

Program 20: 4-BIT UNSIGNED DOWN COUNTER WITH SYNCHRONUOS SET

module counter (clk, s, q);

input clk, s;

output [3:0] q;

reg [3:0] tmp;

always @(posedge clk)

begin

if (s)

tmp <= 4'b1111;

else

tmp <= tmp - 1'b1;

end

assign q = tmp;

endmodule

Program 21: 4-BIT UNSIGNED UP COUNTER WITH AN ASYNCHRONOUS LOAD FROM THE PRIMARY INPUT.

module counter (clk, load, d, q);

input clk, load;

input [3:0] d;

output [3:0] q;

reg [3:0] tmp;

always @(posedge clk or posedge load)

begin

if (load)

tmp <= d;

else

tmp <= tmp + 1'b1;

end

assign q = tmp;

endmodule

Program 22: 4-BIT UNSIGNED UP COUNTER WITH A SYNCHRONOUS LOAD WITH A CONSTANT.

module counter (clk, sload, q);

input clk, sload;

output [3:0] q;

reg [3:0] tmp;

always @(posedge clk)

begin

if (sload)

tmp <= 4'b1010;

else

tmp <= tmp + 1'b1;

end

assign q = tmp;

endmodule

Program 23: 4-BIT UNSIGNED UP COUNTER WITH AN ASYNCHRONOUS CLEAR AND A CLOCK ENABLE.

module counter (clk, clr, ce, q);

input clk, clr, ce;

output [3:0] q;

reg [3:0] tmp;

always @(posedge clk or posedge clr)

begin

if (clr)

tmp <= 4'b0000;

else if (ce)

tmp <= tmp + 1'b1;

end

assign q = tmp;

endmodule

Program 24: 4-BIT UNSIGNED UP/DOWN COUNTER WITH AN ASYNCHRONOUS CLEAR.

module counter (clk, clr, up_down, q);

input clk, clr, up_down;

output [3:0] q;

reg [3:0] tmp;

always @(posedge clk or posedge clr)

begin

if (clr)

tmp <= 4'b0000;

else if (up_down)

tmp <= tmp + 1'b1;

else

tmp <= tmp - 1'b1;

end

assign q = tmp;

endmodule

Program 25: 4-BIT SIGNED UP COUNTER WITH AN ASYNCHRONOUS RESET.

module counter (clk, clr, q);

input clk, clr;

output signed [3:0] q;

reg signed [3:0] tmp;

always @ (posedge clk or posedge clr)

begin

if (clr)

tmp <= 4'b0000;

else

tmp <= tmp + 1'b1;

end

assign q = tmp;

endmodule

Program 26: 4-BIT SIGNED UP COUNTER WITH AN ASYNCHRONOUS RESET AND A MODULO MAXIMUM.

module counter (clk, clr, q);

parameter MAX_SQRT = 4, MAX = (MAX_SQRT*MAX_SQRT);

input clk, clr;

output [MAX_SQRT-1:0] q;

reg [MAX_SQRT-1:0] cnt;

always @ (posedge clk or posedge clr)

begin

if (clr)

cnt <= 0;

else

cnt <= (cnt + 1) %MAX;

end

assign q = cnt;

endmodule

Program 27: 4-BIT UNSIGNED UP ACCUMULATOR WITH AN ASYNCHRONOUS CLEAR.

module accum (clk, clr, d, q);

input clk, clr;

input [3:0] d;

output [3:0] q;

reg [3:0] tmp;

always @(posedge clk or posedge clr)

begin

if (clr)

tmp <= 4'b0000;

else

tmp <= tmp + d;

end

assign q = tmp;

endmodule

Program 28: 8-BIT SHIFT-LEFT REGISTER WITH A POSITIVE-EDGE CLOCK, SERIAL IN AND SERIAL OUT.

module shift (clk, si, so);

input clk,si;

output so;

reg [7:0] tmp;

always @(posedge clk)

begin

tmp <= tmp << 1;

tmp[0] <= si;

end

assign so = tmp[7];

endmodule

Program 29: 8-BIT SHIFT-LEFT REGISTER WITH A NEGATIVE-EDGE CLOCK, A CLOCK ENABLE, A SERIAL IN AND A SERIAL OUT.

module shift (clk, ce, si, so);

input clk, si, ce;

output so;

reg [7:0] tmp;

always @(negedge clk)

begin

if (ce) begin

tmp <= tmp << 1;

tmp[0] <= si;

end

assign so = tmp[7];

endmodule

Program 30: 8-BIT SHIFT-LEFT REGISTER WITH A POSITIVE-EDGE CLOCK, ASYNCHRONOUS CLEAR, SERIAL IN AND SERIAL OUT.

module shift (clk, clr, si, so);

input clk, si, clr;

output so;

reg [7:0] tmp;

always @(posedge clk or posedge clr)

begin

if (clr)

tmp <= 8'b00000000;

else

tmp <= {tmp[6:0], si};

end

assign so = tmp[7];

endmodule

Program 31: 8-BIT SHIFT-LEFT REGISTER WITH A POSITIVE-EDGE CLOCK, A SYNCHRONOUS SET, A SERIAL IN AND A SERIAL OUT.

module shift (clk, s, si, so);

input clk, si, s;

output so;

reg [7:0] tmp;

always @(posedge clk)

begin

if (s)

tmp <= 8'b11111111;

else

tmp <= {tmp[6:0], si};

end

assign so = tmp[7];

endmodule

Program 32: 8-BIT SHIFT-LEFT REGISTER WITH A POSITIVE-EDGE CLOCK, A SERIAL IN AND A PARALLEL OUT.

module shift (clk, si, po);

input clk, si;

output [7:0] po;

reg [7:0] tmp;

always @(posedge clk)

begin

tmp <= {tmp[6:0], si};

end

assign po = tmp;

endmodule

Program 33: 8-BIT SHIFT-LEFT REGISTER WITH A POSITIVE-EDGE CLOCK, AN ASYNCHRONOUS PARALLEL LOAD, A SERIAL IN AND A SERIAL OUT.

module shift (clk, load, si, d, so);

input clk, si, load;

input [7:0] d;

output so;

reg [7:0] tmp;

always @(posedge clk or posedge load)

begin

if (load)

tmp <= d;

else

tmp <= {tmp[6:0], si};

end

assign so = tmp[7];

endmodule

Program 34: 8-BIT SHIFT-LEFT REGISTER WITH A POSITIVE-EDGE CLOCK, A SYNCHRONOUS PARALLEL LOAD, A SERIAL IN AND A SERIAL OUT.

module shift (clk, sload, si, d, so);

input clk, si, sload;

input [7:0] d;

output so;

reg [7:0] tmp;

always @(posedge clk)

begin

if (sload)

tmp <= d;

else

tmp <= {tmp[6:0], si};

end

assign so = tmp[7];

endmodule

Program 35: 8-BIT SHIFT-LEFT/SHIFT-RIGHT REGISTER WITH A POSITIVE-EDGE CLOCK, A SERIAL IN AND A SERIAL OUT.

module shift (clk, si, left_right, po);

input clk, si, left_right;

output po;

reg [7:0] tmp;

always @(posedge clk)

begin

if (left_right == 1'b0)

tmp <= {tmp[6:0], si};

else

tmp <= {si, tmp[7:1]};

end

assign po = tmp;

endmodule

VLSI ON NET

VERILOG

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