FLOATING POINT MULTIPLIER SOURCE CODE

PROJECT 1:      Floating Point Multiplier

LANGUAGE:      VHDL

STATUS:             STABLE (SYNTHESIZED)        

                                         CODE

library IEEE;
use IEEE.numeric_std.all;
use IEEE.std_logic_1164.all;

entity FLPTR is
  port(CLK, St: in std_logic;
       F1, E1, F2, E2: in unsigned(3 downto 0);
       F: out unsigned(6 downto 0);
       E: out unsigned(4 downto 0);
       V, done: out std_logic);
end FLPTR;

architecture BEHAVE of FLPTR is

signal A, B, C: unsigned(3 downto 0);
signal compout, addout: unsigned(3 downto 0);
alias M: std_logic is B(0);
signal X, Y: unsigned(4 downto 0);   
signal Load, Adx, SM8, RSF, LSF: std_logic;
signal AdSh, Sh, Cm, Mdone: std_logic;
signal PS1, NS1: integer range 0 to 3;
signal State, Nextstate: integer range 0 to 4;
begin
main_control: process(PS1, St , Mdone, X, A, B)
  begin
    Load <= '0'; Adx <= '0'; NS1 <= 0; SM8 <= '0';
    RSF <= '0'; LSF <= '0'; V <= '0'; done <= '0';
case PS1 is
      when 0 =>
        if St = '1' then
          Load <= '1';
          NS1 <= 1;
        end if;
      when 1 =>
        Adx <= '1';
        NS1 <= 2;
     
when 2 =>
        if Mdone = '1' then
          if A = 0 then 
            SM8 <= '1';
          elsif A = 4 and B = 0 then
            RSF <= '1';
          elsif A(2) = A(1) then
            LSF <= '1';
          end if;
          NS1 <= 3;
        else
          NS1 <= 2;
        end if;
when 3 =>
        done <= '1';
        if X(4) /= X(3) then
          V <= '1';
        end if;
        if ST = '0' then
          NS1 <= 0;
        end if;
      end case;
  end process main_control;
 
 
  mul2c: process(State, Adx, M)
  begin
    AdSh <= '0'; Sh <= '0'; Cm <= '0'; Mdone <= '0';
    Nextstate <= 0;
    case State is
      when 0 => 
        if Adx = '1' then
          if M = '1' then
            AdSh <= '1';
          else
            Sh <= '1';
          end if;
          Nextstate <= 1;
        end if;
when 1 | 2 =>
        if M = '1' then
          AdSh <= '1';
        else
          Sh <= '1';
        end if;
        Nextstate <= State + 1;
when 3 =>
        if M = '1' then
          Cm <= '1';
          AdSh <= '1';
        else
          Sh <='1';
        end if;
        Nextstate <= 4;
      when 4 =>
        Mdone <= '1'; 
        Nextstate <= 0;
    end case;
   
   
  end process mul2c;
compout <= not C when Cm = '1' else C;
  addout <= A + compout + ("000" & Cm);
  datapath: process(CLK)
  begin
    if CLK = '1' and CLK'event then
      PS1 <= NS1;
      State <= Nextstate;
      if Load = '1' then
        X <= E1(3) & E1;
        Y <= E2(3) & E2;
        A <= "0000";
        B <= F2;
        C <= F1;
      end if;
        if ADX = '1' then
        X <= X + Y;
      end if;
      if SM8 = '1' then
        X <= "11000";
      end if;
   
if RSF = '1' then
        A <= '0' & A(3 downto 1);
        B <= A(0) & B(3 downto 1);
        X <= X + 1;
      end if;
      if LSF = '1' then
        A <= A(2 downto 0) & B(3);
        B <= B(2 downto 0) & '0';
        X <= X - 1;
      end if;
if AdSh = '1' then
        A <= compout(3) & addout(3 downto 1);
        B <= addout(0) & B(3 downto 1);
      end if; 
      if Sh = '1' then
        A <= A(3) & A(3 downto 1);
        B <= A(0) & B(3 downto 1);
      end if;
    end if;
  end process datapath;
 
  F <= A(2 downto 0) & B; 
  E <= X;    
end BEHAVE;