ALTERA DIGITAL LAB SOLUTIONS (DE1 Board)

Laboratory Exercise 2

Numbers and Displays

PART 1:

PROGRAM:

module part1(S0,S1,S2,S3,out);

input [2:0]S0,S1,S2,S3;

output [6:0]out;

logic [6:0]out;

assign out = (S3?(S2?(S1?(S0?(7'b1111111):(7'b1111111)):(S0?(7'b1111111):(7'b1111111))):(S1?(S0?(7'b1111111):(7'b1111111)):(S0?(7'b0011000):(7'b000000)))):(S2?(S1?(S0?(7'b1111000):(7'b0000010)):(S0?(7'b0010010) : (7'b0011001))) : (S1? (S0? (7'b0110000) : (7'b0100100)) : (S0? (7'b1111001): (7'b1000000)))));

endmodule

TEST BENCH:

module part1_tb();

logic [2:0]S0,S1,S2,S3;

logic [6:0]out;

part1 p1(S0,S1,S2,S3,out);

initial begin

S0=1'b0; S1=1'b0; S2=1'b0; S3=1'b0;

#5;

S0=1'b0; S1=1'b0; S2=1'b1; S3=1'b0;

#5;

S0=1'b1; S1=1'b0; S2=1'b1; S3=1'b0;

#5;

S0=1'b1; S1=1'b1; S2=1'b0; S3=1'b1;

end

initial begin

$monitor($time," out= %b", out);

#50 $finish;

end
endmodule

PART 2:

PROGRAM:

module part2(v,d0,d1,z,m,a,b);

input [3:0]v;
output [6:0]d0,d1;
output [3:0]m;
output [2:0]a;
output [6:0]b;
output z;

logic [7:0]d;
logic [3:0]m;
logic [2:0]a;
logic z;

assign z = ((v>4'b1001)?(1'b1):(1'b0));

assign a = (v[2]?(v[1]?(v[0]?(3'b101):(3'b100)):(v[0]?(3'b011):(3'b010))):(v[1]?(v[0]?(3'b001):(3'b000)):(v[0]?(3'b0):(3'b0))));

assign m[3] = (~z&v[3])|(z&1'b0);
assign m[2] = (~z&v[2])|(z&a[2]);
assign m[1] = (~z&v[1])|(z&a[1]);
assign m[0] = (~z&v[0])|(z&a[0]);

assign d0 = (m[3]?(m[2]?(m[1]?(m[0]?(7'b1111111):(7'b1111111)):(m[0]?(7'b1111111):(7'b1111111))):(m[1]?(m[0]?(7'b1111111):(7'b1111111)):(m[0]?(7'b0011000):(7'b0000000)))):(m[2]?(m[1]?(m[0]?(7'b1111000):(7'b0000010)):(m[0]?(7'b0010010) : (7'b0011001))) : (m[1]? (m[0]? (7'b0110000) : (7'b0100100)) : (m[0]? (7'b1111001): (7'b1000000)))));

assign b = z?7'b1111001:7'b1111111;

assign d1 = b;
endmodule

TEST BENCH:

module part2_tb();

logic [3:0]v;
logic [6:0]d0,d1;
logic [3:0]m;
logic [2:0]a;
logic [6:0]b;
logic z;

part2 p2(v,d0,d1,z,m,a,b);

initial begin
v[3]=0; v[2]=0; v[1]=0; v[0]=0;

#5 v[3]=0; v[2]=1; v[1]=1; v[0]=0;

#5 v[3]=1; v[2]=1; v[1]=0; v[0]=0;
#5;
end

initial begin
$monitor($time,"z = %b, a = %b, m = %b, v=%d, d0=%b d1=%b",z,a,m,v,d0,d1);
#50 $finish;
end
endmodule

PART 3:

PROGRAM:

module part3(a,b,cin,s,c,co);

input [3:0]a,b;
input cin;
output [3:0]s;
output [3:0]c;
output co;
int i;

logic [3:0]s,c;
logic co;

always@(a,b,cin) begin
c[0] = cin;

for(i=0;i<4;i=i+1) begin
s[i] = ((a[i]^b[i])^c[i]);
c[i+1] = (~(a[i]^b[i])&b[i])|((a[i]^b[i])&c[i]);
end
end
assign co = c[3];
endmodule

TEST BENCH:

module part3_tb();

logic [3:0]a,b,s;
logic [3:0]c;
logic cin,co;

part3 p3(a,b,cin,s,c,co);

initial begin
a=4'b0000; b=4'b0000; cin=1'b0;

#5 a=4'b1101; b=4'b0101;

end

initial begin
$monitor($time," s=%b c=%b", s,co);

#100 $finish;
end

endmodule

PART 4:

PROGRAM:

module part4(a,b,s,cin,c,co,x,y,d0,d1,m);

input [3:0]a,b;
input cin;

output [3:0]c,x,m,s;
logic [3:0]c,x,m,s;

output co;
logic co;

output [6:0]d0,d1,y;
logic [6:0]d0,d1,y;

int i;

always@(a,b,cin) begin
c[0] = cin;

for(i=0;i<4;i=i+1) begin
s[i] = ((a[i]^b[i])^c[i]);
c[i+1] = (~(a[i]^b[i])&b[i])|((a[i]^b[i])&c[i]);
end
end


assign co = c[3];

assign x  = (s[3]?(s[2]?(s[1]?(s[0]?(4'b0000):(4'b0000)):(s[0]?(4'b0000):(4'b0000))):(s[1]?(s[0]?(4'b0000):(4'b0000)):(s[0]?(4'b0000):(4'b0000)))):(s[2]?(s[1]?(s[0]?(4'b1001):(4'b1000)):(s[0]?(4'b0111):(4'b0110))):(s[1]?(s[0]?(4'b0000):(4'b0000)):(s[0]?(4'b0000):(4'b0000)))));

assign m[3] = (~co&s[3])|(co&x[3]);
assign m[2] = (~co&s[2])|(co&x[2]);
assign m[1] = (~co&s[1])|(co&x[1]);
assign m[0] = (~co&s[0])|(co&x[0]);

assign d0 = (m[3]?(m[2]?(m[1]?(m[0]?(7'b1111111):(7'b1111111)):(m[0]?(7'b1111111):(7'b1111111))):(m[1]?(m[0]?(7'b1111111):(7'b1111111)):(m[0]?(7'b0011000):(7'b0000000)))):(m[2]?(m[1]?(m[0]?(7'b1111000):(7'b0000010)):(m[0]?(7'b0010010) : (7'b0011001))) : (m[1]? (m[0]? (7'b0110000) : (7'b0100100)) : (m[0]? (7'b1111001): (7'b1000000)))));

assign y  = co?7'b1111001:7'b1111111;

assign d1 = y;

endmodule

TEST BENCH:

module part4_tb();

logic [3:0]a,b;
logic cin;

logic [3:0]c,x,m,s;
logic co;
logic [6:0]d0,d1,y;

part4 p4(a,b,s,cin,c,co,x,y,d0,d1,m);

initial begin

a=4'b0010; b=4'b0100; cin = 0;

#5 a=4'b0010; b=4'b0100;

#5 a=4'b1001; b=4'b1001;

end

initial begin

$monitor($time," d0=%b d1=%b", d0,d1);
#100 $finish;

end
endmodule

PART 5:

PROGRAM:

module part5(a,b,cin,s0,s1,c0,t,z);

input [3:0]a,b; 
input cin;        

output [3:0]s0,s1;
logic [3:0]s0,s1; 

output c0;
logic c0;       
   
output [3:0]z;
logic [3:0]z;

     
output [4:0]t;
logic [4:0]t; 

always @(a,b,cin)
begin
t=a+b+cin;
if(t > 9)begin
z=10;
c0=1;  
end
else begin
z=0;
c0=0;
end
s0 = t - z;
s1 = c0;
end
endmodule 

TEST BENCH:

module part5_tb();

logic [3:0]a,b,s0,s1,z;
logic [4:0]t;
logic c0,cin;

part5 p5(a,b,cin,s0,s1,c0,t,z);

initial begin
a=4'b0000; b=4'b0000; cin=1'b0;

#5 a=4'b1000; b=4'b0001; cin=1'b0;

a=4'b1000; b=4'b0100; cin=1'b0;

end

initial begin

$monitor($time," s0=%b s1=%b", s0, s1);
#50 $finish;
end
endmodule

PART 6:

PROGRAM:

module part6(a,s0,s1,c1,c2,c3,c4,d1,d2,d3,d4);
input [5:0]a;
output [3:0]s0,s1;

output [3:0] c1,c2,c3,c4;
logic [3:0] c1,c2,c3,c4;

output [3:0] d1,d2,d3,d4;
logic [3:0] d1,d2,d3,d4;


    assign d1 = {1'b0,a[5:3]};
    assign d2 = {c1[2:0],a[2]};
    assign d3 = {c2[2:0],a[1]};
    add3 m1(d1,c1);
    add3 m2(d2,c2);
    add3 m3(d3,c3);
    assign s0 = {c3[2:0],a[0]};
    assign s1 = {1'b0,c1[3],c2[3],c3[3]};

endmodule

module add3(in,out);
input [3:0] in;
output [3:0] out;
logic [3:0] out;

always @ (in)
      case (in)
      4'b0000: out <= 4'b0000;
      4'b0001: out <= 4'b0001;
      4'b0010: out <= 4'b0010;
      4'b0011: out <= 4'b0011;
      4'b0100: out <= 4'b0100;
      4'b0101: out <= 4'b1000;
      4'b0110: out <= 4'b1001;
      4'b0111: out <= 4'b1010;
      4'b1000: out <= 4'b1011;
      4'b1001: out <= 4'b1100;
      default: out <= 4'b0000;
      endcase
endmodule

TEST BENCH:

module part6_tb();

logic [5:0]a;
logic [3:0]s0,s1,c1,c2,c3,c4,d1,d2,d3,d4;

part6 p6(a,s0,s1,c1,c2,c3,c4,d1,d2,d3,d4);

initial begin
a=6'b000000;

#5 a=6'b010010;
end

initial begin
$monitor($time," s0=%b s1=%b", s0,s1);
#50 $finish;
end
endmodule