Tuesday, July 01, 2014

LOGIC SYNTHESIS PPT


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Monday, June 30, 2014

ASYNCHRONOUS FIFO

CODE:



module a_fifo5(d_out,f_full_flag,f_half_full_flag,f_empty_flag,

f_almost_full_flag,f_almost_empty_flag,d_in,r_en,w_en,r_clk,w_clk,reset);


parameter f_width=8; //FIFO width

parameter f_depth=16; //FIFO depth

parameter f_ptr_width=4; //because depth =16;

parameter f_half_full_value=8;

parameter f_almost_full_value=14;

parameter f_almost_empty_value=2;


output [f_width-1:0] d_out; reg [f_width-1:0] d_out; //outputs

output f_full_flag,f_half_full_flag,f_almost_full_flag,f_empty_flag,f_almost_empty_flag;


input [f_width-1:0] d_in;

input r_en,w_en,r_clk,w_clk;

input reset;


//internal registers,wires

wire [f_ptr_width-1:0] r_ptr,w_ptr;

reg r_next_en,w_next_en;

reg [f_ptr_width-1:0] ptr_diff;


reg [f_width-1:0] f_memory[f_depth-1:0];


assign f_full_flag=(ptr_diff==(f_depth-1)); //assign FIFO status

assign f_empty_flag=(ptr_diff==0);

assign f_half_full_flag=(ptr_diff==f_half_full_value);

assign f_almost_full_flag=(ptr_diff==f_almost_full_value);

assign f_almost_empty_flag=(ptr_diff==f_almost_empty_value);


//---------------------------------------------------------

always @(posedge w_clk) //write to memory

begin

if(w_en) begin

if(!f_full_flag)

f_memory[w_ptr]<=d_in; end

end


//---------------------------------------------------------

always @(posedge r_clk) //read from memory

begin

if(reset)

d_out<=0; //f_memory[r_ptr];

else if(r_en) begin

if(!f_empty_flag)

d_out<=f_memory[r_ptr]; end

else d_out<=0;

end


//---------------------------------------------------------

always @(*) //ptr_diff changes as read or write clock change

begin

if(w_ptr>r_ptr)

ptr_diff<=w_ptr-r_ptr;

else if(w_ptr

begin

ptr_diff<=((f_depth-r_ptr)+w_ptr);

end

else ptr_diff<=0;

end


//---------------------------------------------------------

always @(*) //after empty flag activated fifo read counter should not increment;

begin if(r_en && (!f_empty_flag))

r_next_en=1;

else r_next_en=0;

end

//--------------------------------------------------------


always @(*) //after full flag activated fifo write counter should not increment;

begin if(w_en && (!f_full_flag))

w_next_en=1;

else w_next_en=0;

end


//---------------------------------------------------------

b_counter //instantiate address counters r_b_counter(.c_out(r_ptr),.c_reset(reset),.c_clk(r_clk),.en(r_next_en));

b_counter w_b_counter(.c_out(w_ptr),.c_reset(reset),.c_clk(w_clk),.en(w_next_en));

endmodule


//==============================================================

//b_counter.v; 4 bit asynchronous binary up counter

//==============================================================

module b_counter(c_out,c_reset,c_clk,en);


parameter c_width=4; //counter width


output [c_width-1:0] c_out; reg [c_width-1:0] c_out;

input c_reset,c_clk,en;


always @(posedge c_clk or posedge c_reset)

if (c_reset)

c_out <= 0;

else if(en)

c_out <= c_out + 1;

endmodule

//===========================================================


//===========================================================

//fifo_top.v; top level verilog code of FIFO

//To be used with Xilinx ISE-simulation and synthesis

//For functional simulation this module is not necessary

//============================================================

module fifo_top(x,y,z,d_out,f_full_flag,f_half_full_flag,f_empty_flag,

f_almost_full_flag,f_almost_empty_flag,d_in,r_en,w_en,CLKIN_IN,RST_IN,reset);


parameter f_width=8;

parameter f_depth=16;

parameter f_ptr_width=4;

parameter f_half_full_value=8;

parameter f_almost_full_value=14;

parameter f_almost_empty_value=2;


output [f_width-1:0] d_out; //reg [f_width-1:0] d_out; //outputs

output f_full_flag,f_half_full_flag,f_almost_full_flag,f_empty_flag,f_almost_empty_flag;

output x,y,z;

input [f_width-1:0] d_in;

input r_en,w_en,CLKIN_IN,RST_IN;

input reset;


a_fifo5 a_fifo55(d_out,f_full_flag,f_half_full_flag,f_empty_flag,

f_almost_full_flag,f_almost_empty_flag,d_in,r_en,w_en,CLK0_OUT,CLKDV_OUT,reset); //instantiate fifo


dcm_fifo dcm_fifo1(CLKIN_IN,RST_IN,CLKDV_OUT,CLKFX_OUT,CLKIN_IBUFG_OUT,CLK0_OUT, LOCKED_OUT); //instantiate DCM

assign x=CLKIN_IBUFG_OUT; //simply to avoid error

assign y=LOCKED_OUT;

assign z=CLKFX_OUT;


endmodule
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SYNCHRONOUS FIFO

CODE:



     // Design Name : syn_fifo
    // File Name   : syn_fifo.v
    // Function    : Synchronous (single clock) FIFO
 
   module syn_fifo (
   clk      , // Clock input
   rst      , // Active high reset
   wr_cs    , // Write chip select
   rd_cs    , // Read chipe select
   data_in  , // Data input
   rd_en    , // Read enable
   wr_en    , // Write Enable
   data_out , // Data Output
   empty    , // FIFO empty
   full       // FIFO full
   );    
    
   // FIFO constants
   parameter DATA_WIDTH = 8;
   parameter ADDR_WIDTH = 8;
   parameter RAM_DEPTH = (1 << ADDR_WIDTH);
   // Port Declarations
   input clk ;
   input rst ;
   input wr_cs ;
   input rd_cs ;
   input rd_en ;
   input wr_en ;
   input [DATA_WIDTH-1:0] data_in ;
   output full ;
   output empty ;
   output [DATA_WIDTH-1:0] data_out ;
   
   //-----------Internal variables-------------------
   reg [ADDR_WIDTH-1:0] wr_pointer;
   reg [ADDR_WIDTH-1:0] rd_pointer;
   reg [ADDR_WIDTH :0] status_cnt;
   reg [DATA_WIDTH-1:0] data_out ;
   wire [DATA_WIDTH-1:0] data_ram ;
   
   //-----------Variable assignments---------------
   assign full = (status_cnt == (RAM_DEPTH-1));
   assign empty = (status_cnt == 0);
   
   //-----------Code Start---------------------------
   always @ (posedge clk or posedge rst)
   begin : WRITE_POINTER
     if (rst) begin
       wr_pointer <= 0;
     end else if (wr_cs && wr_en ) begin
       wr_pointer <= wr_pointer + 1;
     end
   end
   
   always @ (posedge clk or posedge rst)
   begin : READ_POINTER
     if (rst) begin
       rd_pointer <= 0;
     end else if (rd_cs && rd_en ) begin
       rd_pointer <= rd_pointer + 1;
     end
   end
   
   always  @ (posedge clk or posedge rst)
   begin : READ_DATA
     if (rst) begin
       data_out <= 0;
     end else if (rd_cs && rd_en ) begin
       data_out <= data_ram;
     end
   end
   
   always @ (posedge clk or posedge rst)
   begin : STATUS_COUNTER
     if (rst) begin
       status_cnt <= 0;
     // Read but no write.
     end else if ((rd_cs && rd_en) &&  ! (wr_cs && wr_en) 
                   && (status_cnt  ! = 0)) begin
       status_cnt <= status_cnt - 1;
     // Write but no read.
     end else if ((wr_cs && wr_en) &&  ! (rd_cs && rd_en) 
                  && (status_cnt  ! = RAM_DEPTH)) begin
       status_cnt <= status_cnt + 1;
     end
   end 
      
   ram_dp_ar_aw #(DATA_WIDTH,ADDR_WIDTH)DP_RAM (
   .address_0 (wr_pointer) , // address_0 input 
   .data_0    (data_in)    , // data_0 bi-directional
   .cs_0      (wr_cs)      , // chip select
   .we_0      (wr_en)      , // write enable
   .oe_0      (1'b0)       , // output enable
   .address_1 (rd_pointer) , // address_q input
   .data_1    (data_ram)   , // data_1 bi-directional
   .cs_1      (rd_cs)      , // chip select
   .we_1      (1'b0)       , // Read enable
   .oe_1      (rd_en)        // output enable
   );     
  
  endmodule
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PERL BASICS

1.What is Perl?

     Perl is a general-purpose programming language originally developed for text manipulation and now used for a wide range of tasks including system administration, web development, network programming, GUI development, and more.
     The language is intended to be practical (easy to use, efficient, complete) rather than beautiful (tiny, elegant, minimal). Its major features are that it's easy to use, supports both procedural and object-oriented (OO) programming, has powerful built-in support for text processing, and has one of the world's most impressive collections of third-party modules.

2.Running Perl programs

To run a Perl program from the Unix command line:

                 perl file_name.pl

 First line of the script contains:

                       #!/usr/bin/perl (-w -s )
                             or
                        use warning;
                        use strict;

    w ->  It is used for the warning. This pops out  the message if program
              contains any error or warning.
    s -> This is used to caught the potential problem in the program.


3.Basic syntax

A Perl script or program consists of one or more statements. These statements are simply written in the script in a straightforward fashion. There is no need to have a main() function or anything of that kind.

Perl statements end in a semi-colon:

                      print " Message " ;

print -> Like "C" print is a inbuilt function, which displays the Message  on the 
              GUI (terminal).

Example:  print "Hello World";

Numbers don't need quotes around them:

                Print 25;

4.Perl variable types

 Perl has three main variable types: 1.scalars  2.arrays  3.hashes.

a] Scalars:
 
A scalar represents a single value:

               $name = "John";
            $number=25;

Scalar values can be strings, integers or floating point numbers, and Perl will automatically convert between them as required.

Scalar values can be used in various ways:
 
                    print $name;
                 print "My Name is $name\n";
                 print "Square of the $number is" , $number*$number "\n";

There are a number of "magic" scalars with names that look like punctuation or line noise. These special variables are used for all kinds of purposes.The only one you need to know about for now is "$_ " which is the "default variable". It's used as the default argument to a number of functions in Perl, and it's set implicitly by certain looping constructs.
         
                  print;                         # Prints content of $_ by default.


b] Arrays:

An array represents a list of values:

                  @friends = ("John" , "Jimmy", "Lucy") ;
               @numbers=(10,20,30);
               @mixed=("john",20,1.58);

Arrays are zero-indexed. Here's how you get at elements in an array:

                print $friends[0];              #  prints John
                print $numbers[1];           #  prints 20
                print $mixed [2];              # prints 1.58

The special variable $#array tells you the index of the last element of an array:

                print $numbers[$#numbers];   # Prints the last element of the
                                                                            array i.e 30.

You might be tempted to use $#array + 1 to tell you how many items there are in an array. Don't bother. As it happens, using @array where Perl expects to find a scalar value ("in scalar context") will give you the number of elements in the array:

                                      if (@friends <5) 
                                              { ......}

The elements we're getting from the array start with a $ because we're getting just a single value out of the array; you ask for a scalar, you get a scalar.
To get multiple values from an array:
             
                @friends [0,1]                       # Gives "John" and "Jimmy"
             @friends [0..2]                     # Gives "John","Jimmy" and "Lucy"
             @friends [1..$#friends]       # Gives all except 1st one

This is called an "array slice".
You can do various useful things to lists:

                        @sorted = sort @friends;
                    @rev      = reverse @numbers;

There are a couple of special arrays too, such as @ARGV (the command line arguments to your script) and @_ (the arguments passed to a subroutine).
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Sunday, June 29, 2014

ALTERA DIGITAL LAB SOLUTIONS (DE1 Board)

Laboratory Exercise 3

Latches, Flip-flops, and Registers



PART 1:


PROGRAM:

module part1(clk,r,s,q);

input clk,r,s;

output [1:0]q;

logic a,b;


assign a = (clk&r);
assign b = (clk&s);

assign q[0] = ~(q[1]|a);
assign q[1] = ~(q[0]|b);
endmodule

TEST BENCH:

module part1_tb();

logic clk,r,s;
logic [1:0]q;

part1 p1(clk,r,s,q);
initial
clk=0;
always  #4 clk=~clk;


initial begin
r=0; s=0;
#5;
 r=1; s=0;
#5;
r=0; s=1;
#5;
r=1; s=1;
end

initial begin
$monitor ("r=%b,s=%b,clk=%b,q[0]=%b,q[1]=%b",r,s,clk,q[0],q[1]);
#100 $finish;
end
endmodule



PART 2:

PROGRAM:

module part2(clk,d,q);

input clk,d;
output [1:0]q;

logic a,b;

assign a = ~(clk&d);
assign b = ~(clk&~d);

assign q[0] = ~(a&q[1]);
assign q[1] = ~(b&q[0]);

endmodule


TEST BENCH:

module part2_tb();

logic clk,d;
logic [1:0]q;

ppart2 p3(clk,d,q);

initial
clk=0;
always #4 clk=~clk;

initial begin
d=0;
#10;
d=1;
end

initial begin
$monitor("d=%b,q[0]=%b,q[1]=%b",d,q[0],q[1]);
#50 $finish;
end
endmodule



PART 3:

PROGRAM:

///////Main Program/////

module part3(clk,d,q1,q2);
input clk,d;
output q1,q2;

wire c;

p_comp a1(~clk,d,c);
p_comp a2(clk,c,q1);

assign q2=~q1;

endmodule

///// component ///////

module p_comp(clk,d,q);

input clk,d;
output [1:0]q;

logic a,b;

assign a = ~(clk&d);
assign b = ~(clk&~d);

assign q[0] = ~(a&q[1]);
assign q[1] = ~(b&q[0]);
endmodule

TEST BENCH:

module part3_tb();

 reg clk,d;
 wire q1,q2;

part3 p1(clk,d,q1,q2);

initial
begin
d=0;
clk=0;
end
always #5 clk=~clk;

always #2 d=~d;

initial
begin
$monitor($time,"clk= %b d=%b,q1=%b,q2=%b",clk,d,q1,q2);
#50 $finish;
end
endmodule



PART 4:

PROGRAM:

module part4(d,clk,b,bbar);

input d,clk;
output  [2:0]b,bbar;

sample a1(d,clk,b[0]);
sample a2(d,clk,b[1]);
sample a3(d,~clk,b[2]);

assign bbar[0] = ~b[0];

assign bbar[1] = ~b[1];

assign bbar[2] = ~b[2];

endmodule


TEST BENCH:

module part4_tb();

reg d,clk;

wire [2:0]b;

part4 d1(d,clk,b,bbar);

initial begin

clk=0; d=0;

#5 d=1;
end

initial begin
 forever #5 clk=~clk;
end
 
initial begin
$monitor ("clk=%b,d=%b,b[0]=%b,b[1]=%b,b[2]=%b",clk,d,b[0],b[1],b[2]);

#50 $finish;
end
endmodule


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ALTERA DIGITAL LAB SOLUTIONS (DE1 Board)

Laboratory Exercise 2

Numbers and Displays


PART 1:


PROGRAM:

module part1(S0,S1,S2,S3,out);

input [2:0]S0,S1,S2,S3;

output [6:0]out;

logic [6:0]out;

assign out = (S3?(S2?(S1?(S0?(7'b1111111):(7'b1111111)):(S0?(7'b1111111):(7'b1111111))):(S1?(S0?(7'b1111111):(7'b1111111)):(S0?(7'b0011000):(7'b000000)))):(S2?(S1?(S0?(7'b1111000):(7'b0000010)):(S0?(7'b0010010) : (7'b0011001))) : (S1? (S0? (7'b0110000) : (7'b0100100)) : (S0? (7'b1111001): (7'b1000000)))));

endmodule


TEST BENCH:
module part1_tb();

logic [2:0]S0,S1,S2,S3;

logic [6:0]out;

part1 p1(S0,S1,S2,S3,out);

initial begin

S0=1'b0; S1=1'b0; S2=1'b0; S3=1'b0;

#5;

S0=1'b0; S1=1'b0; S2=1'b1; S3=1'b0;

#5;

S0=1'b1; S1=1'b0; S2=1'b1; S3=1'b0;

#5;

S0=1'b1; S1=1'b1; S2=1'b0; S3=1'b1;

end

initial begin

$monitor($time," out= %b", out);

#50 $finish;

end
endmodule



PART 2:

PROGRAM:

module part2(v,d0,d1,z,m,a,b);

input [3:0]v;
output [6:0]d0,d1;
output [3:0]m;
output [2:0]a;
output [6:0]b;
output z;

logic [7:0]d;
logic [3:0]m;
logic [2:0]a;
logic z;

assign z = ((v>4'b1001)?(1'b1):(1'b0));

assign a = (v[2]?(v[1]?(v[0]?(3'b101):(3'b100)):(v[0]?(3'b011):(3'b010))):(v[1]?(v[0]?(3'b001):(3'b000)):(v[0]?(3'b0):(3'b0))));

assign m[3] = (~z&v[3])|(z&1'b0);
assign m[2] = (~z&v[2])|(z&a[2]);
assign m[1] = (~z&v[1])|(z&a[1]);
assign m[0] = (~z&v[0])|(z&a[0]);

assign d0 = (m[3]?(m[2]?(m[1]?(m[0]?(7'b1111111):(7'b1111111)):(m[0]?(7'b1111111):(7'b1111111))):(m[1]?(m[0]?(7'b1111111):(7'b1111111)):(m[0]?(7'b0011000):(7'b0000000)))):(m[2]?(m[1]?(m[0]?(7'b1111000):(7'b0000010)):(m[0]?(7'b0010010) : (7'b0011001))) : (m[1]? (m[0]? (7'b0110000) : (7'b0100100)) : (m[0]? (7'b1111001): (7'b1000000)))));

assign b = z?7'b1111001:7'b1111111;

assign d1 = b;
endmodule


TEST BENCH:


module part2_tb();

logic [3:0]v;
logic [6:0]d0,d1;
logic [3:0]m;
logic [2:0]a;
logic [6:0]b;
logic z;

part2 p2(v,d0,d1,z,m,a,b);

initial begin
v[3]=0; v[2]=0; v[1]=0; v[0]=0;

#5 v[3]=0; v[2]=1; v[1]=1; v[0]=0;

#5 v[3]=1; v[2]=1; v[1]=0; v[0]=0;
#5;
end

initial begin
$monitor($time,"z = %b, a = %b, m = %b, v=%d, d0=%b d1=%b",z,a,m,v,d0,d1);
#50 $finish;
end
endmodule



PART 3:

PROGRAM:

module part3(a,b,cin,s,c,co);

input [3:0]a,b;
input cin;
output [3:0]s;
output [3:0]c;
output co;
int i;

logic [3:0]s,c;
logic co;

always@(a,b,cin) begin
c[0] = cin;

for(i=0;i<4;i=i+1) begin
s[i] = ((a[i]^b[i])^c[i]);
c[i+1] = (~(a[i]^b[i])&b[i])|((a[i]^b[i])&c[i]);
end
end
assign co = c[3];
endmodule

TEST BENCH:

module part3_tb();

logic [3:0]a,b,s;
logic [3:0]c;
logic cin,co;

part3 p3(a,b,cin,s,c,co);

initial begin
a=4'b0000; b=4'b0000; cin=1'b0;

#5 a=4'b1101; b=4'b0101;

end

initial begin
$monitor($time," s=%b c=%b", s,co);

#100 $finish;
end

endmodule



PART 4:

PROGRAM:

module part4(a,b,s,cin,c,co,x,y,d0,d1,m);

input [3:0]a,b;
input cin;

output [3:0]c,x,m,s;
logic [3:0]c,x,m,s;

output co;
logic co;

output [6:0]d0,d1,y;
logic [6:0]d0,d1,y;

int i;

always@(a,b,cin) begin
c[0] = cin;

for(i=0;i<4;i=i+1) begin
s[i] = ((a[i]^b[i])^c[i]);
c[i+1] = (~(a[i]^b[i])&b[i])|((a[i]^b[i])&c[i]);
end
end


assign co = c[3];

assign x  = (s[3]?(s[2]?(s[1]?(s[0]?(4'b0000):(4'b0000)):(s[0]?(4'b0000):(4'b0000))):(s[1]?(s[0]?(4'b0000):(4'b0000)):(s[0]?(4'b0000):(4'b0000)))):(s[2]?(s[1]?(s[0]?(4'b1001):(4'b1000)):(s[0]?(4'b0111):(4'b0110))):(s[1]?(s[0]?(4'b0000):(4'b0000)):(s[0]?(4'b0000):(4'b0000)))));

assign m[3] = (~co&s[3])|(co&x[3]);
assign m[2] = (~co&s[2])|(co&x[2]);
assign m[1] = (~co&s[1])|(co&x[1]);
assign m[0] = (~co&s[0])|(co&x[0]);

assign d0 = (m[3]?(m[2]?(m[1]?(m[0]?(7'b1111111):(7'b1111111)):(m[0]?(7'b1111111):(7'b1111111))):(m[1]?(m[0]?(7'b1111111):(7'b1111111)):(m[0]?(7'b0011000):(7'b0000000)))):(m[2]?(m[1]?(m[0]?(7'b1111000):(7'b0000010)):(m[0]?(7'b0010010) : (7'b0011001))) : (m[1]? (m[0]? (7'b0110000) : (7'b0100100)) : (m[0]? (7'b1111001): (7'b1000000)))));

assign y  = co?7'b1111001:7'b1111111;

assign d1 = y;

endmodule

TEST BENCH:

module part4_tb();

logic [3:0]a,b;
logic cin;

logic [3:0]c,x,m,s;
logic co;
logic [6:0]d0,d1,y;

part4 p4(a,b,s,cin,c,co,x,y,d0,d1,m);

initial begin

a=4'b0010; b=4'b0100; cin = 0;

#5 a=4'b0010; b=4'b0100;

#5 a=4'b1001; b=4'b1001;

end

initial begin

$monitor($time," d0=%b d1=%b", d0,d1);
#100 $finish;

end
endmodule



PART 5:

PROGRAM:

module part5(a,b,cin,s0,s1,c0,t,z);

input [3:0]a,b; 
input cin;        

output [3:0]s0,s1;
logic [3:0]s0,s1; 

output c0;
logic c0;       
   
output [3:0]z;
logic [3:0]z;

     
output [4:0]t;
logic [4:0]t; 

always @(a,b,cin)
begin
t=a+b+cin;
if(t > 9)begin
z=10;
c0=1;  
end
else begin
z=0;
c0=0;
end
s0 = t - z;
s1 = c0;
end
endmodule 


TEST BENCH:

module part5_tb();

logic [3:0]a,b,s0,s1,z;
logic [4:0]t;
logic c0,cin;

part5 p5(a,b,cin,s0,s1,c0,t,z);

initial begin
a=4'b0000; b=4'b0000; cin=1'b0;

#5 a=4'b1000; b=4'b0001; cin=1'b0;

a=4'b1000; b=4'b0100; cin=1'b0;

end

initial begin

$monitor($time," s0=%b s1=%b", s0, s1);
#50 $finish;
end
endmodule




PART 6:


PROGRAM:

module part6(a,s0,s1,c1,c2,c3,c4,d1,d2,d3,d4);
input [5:0]a;
output [3:0]s0,s1;

output [3:0] c1,c2,c3,c4;
logic [3:0] c1,c2,c3,c4;

output [3:0] d1,d2,d3,d4;
logic [3:0] d1,d2,d3,d4;


    assign d1 = {1'b0,a[5:3]};
    assign d2 = {c1[2:0],a[2]};
    assign d3 = {c2[2:0],a[1]};
    add3 m1(d1,c1);
    add3 m2(d2,c2);
    add3 m3(d3,c3);
    assign s0 = {c3[2:0],a[0]};
    assign s1 = {1'b0,c1[3],c2[3],c3[3]};

endmodule

module add3(in,out);
input [3:0] in;
output [3:0] out;
logic [3:0] out;

always @ (in)
      case (in)
      4'b0000: out <= 4'b0000;
      4'b0001: out <= 4'b0001;
      4'b0010: out <= 4'b0010;
      4'b0011: out <= 4'b0011;
      4'b0100: out <= 4'b0100;
      4'b0101: out <= 4'b1000;
      4'b0110: out <= 4'b1001;
      4'b0111: out <= 4'b1010;
      4'b1000: out <= 4'b1011;
      4'b1001: out <= 4'b1100;
      default: out <= 4'b0000;
      endcase
endmodule

TEST BENCH:

module part6_tb();

logic [5:0]a;
logic [3:0]s0,s1,c1,c2,c3,c4,d1,d2,d3,d4;

part6 p6(a,s0,s1,c1,c2,c3,c4,d1,d2,d3,d4);

initial begin
a=6'b000000;

#5 a=6'b010010;
end

initial begin
$monitor($time," s0=%b s1=%b", s0,s1);
#50 $finish;
end
endmodule


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VERILOG BASICS

Design Methodology:



There are two basic types of digital design methodologies: a top-down design methodology and a bottom-up design methodology.
In a top-down design methodology, we define the top-level block and identify the sub-blocks necessary to build the top-level block. We further subdivide the sub-blocks until we come to leaf cells, which are the cells that cannot further be divided. Figure below shows the top-down design process.

Top Down Approach:
              


Bottom Up Approach:
          

Behavioural or Algorithmic level:

This is the highest level of abstraction provided by the verilog HDL. A module can be implemented in terms of desired design algorithm withouth concern for the hardware implementation details. Designing this level is very similar to “C” programming.

Data flow level:

At this level ,module is designed by specifying the dataflow. The designer is aware of how data flows between hardware registers and how the data is processed in the design.
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